Patents by Inventor Motoaki Wakui
Motoaki Wakui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8692370Abstract: A semiconductor element (10) is secured to an island (7), and a plurality of through-holes (8) are formed in the portion of the island (7), which surrounds the area to which the semiconductor element (10) is secured. Further, the electrode pads of the semiconductor element (10) and leads (4) are electrically connected by copper wires (11). In this structure, the cost of materials is reduced by using the copper wires (11) in comparison with gold wires. Further, a part of a resin package (2) is embedded in through-holes (8), so that the island (7) can be easily supported within the resin package (2).Type: GrantFiled: February 25, 2010Date of Patent: April 8, 2014Assignee: Semiconductor Components Industries, LLCInventors: Takashi Kitazawa, Yasushige Sakamoto, Motoaki Wakui
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Publication number: 20110304046Abstract: A semiconductor element (10) is secured to an island (7), and a plurality of through-holes (8) are formed in the portion of the island (7), which surrounds the area to which the semiconductor element (10) is secured. Further, the electrode pads of the semiconductor element (10) and leads (4) are electrically connected by copper wires (11). In this structure, the cost of materials is reduced by using the copper wires (11) in comparison with gold wires. Further, a part of a resin package (2) is embedded in through-holes (8), so that the island (7) can be easily supported within the resin package (2).Type: ApplicationFiled: February 25, 2010Publication date: December 15, 2011Applicants: ON SEMICONDUCTOR TRADING, LTD. a Bermuda limited company, ON SEMICONDUCTOR TRADING, LTD. a Bermuda limited company, ON SEMICONDUCTOR TRADING, LTD. a Bermuda limited liablity companyInventors: Takashi Kitazawa, Yasushige Sakamoto, Motoaki Wakui
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Patent number: 7919875Abstract: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.Type: GrantFiled: December 13, 2007Date of Patent: April 5, 2011Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductor Co., Ltd.Inventors: Takashi Noma, Katsuhiko Kitagawa, Hisao Otsuka, Akira Suzuki, Yoshinori Seki, Yukihiro Takao, Keiichi Yamaguchi, Motoaki Wakui, Masanori Iida
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Patent number: 7456083Abstract: The invention is directed to an improvement of cutting accuracy in a cutting process when a semiconductor device attached with a supporting member is manufactured. The invention provides a manufacturing method of a semiconductor device where a semiconductor wafer attached with a glass substrate is cut with moving a rotation blade along a dicing region and has following features. A pair of alignment marks is formed facing each other over the dicing region on the semiconductor wafer. Then, when the rotation blade is to be aligned on a center of the dicing region, that is, on a centerline thereof in the cutting process, positions of the alignment marks are detected by a recognition camera, the centerline is calculated based on the detection result, and the rotation blade is aligned on the centerline to perform cutting.Type: GrantFiled: March 2, 2005Date of Patent: November 25, 2008Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductor Co., Ltd.Inventors: Takashi Noma, Yoshinori Seki, Motoaki Wakui
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Publication number: 20080093708Abstract: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.Type: ApplicationFiled: December 13, 2007Publication date: April 24, 2008Applicants: SANYO Electric Co., Ltd., Kanto SANYO Semiconductor Co., Ltd.Inventors: Takashi Noma, Katsuhiko Kitagawa, Hisao Otsuka, Akira Suzuki, Yoshinori Seki, Yukihiro Takao, Keiichi Yamaguchi, Motoaki Wakui, Masanori Iida
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Patent number: 7312107Abstract: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.Type: GrantFiled: August 4, 2004Date of Patent: December 25, 2007Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Takashi Noma, Katsuhiko Kitagawa, Hisao Otsuka, Akira Suzuki, Yoshinori Seki, Yukihiro Takao, Keiichi Yamaguchi, Motoaki Wakui, Masanori Iida
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Patent number: 7064046Abstract: The invention provides an algorithm for aligning a rotating blade in a dicing process of partially dicing a wafer attached to a substrate. A width of a cut groove and distance between pads in the cut groove are detected by a recognition camera. Based on a result of this detection, alignment data ?y which is distance between a centerline of the width of the cut groove and a real centerline are calculated. Based on a difference between the distance of the pads in the cut groove and a target value of the distance, data ?z on alignment in a depth direction of the cut groove is calculated. The rotating blade is aligned by using the alignment data ?y and ?z.Type: GrantFiled: February 5, 2004Date of Patent: June 20, 2006Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Motoaki Wakui, Isao Ochiai, Ron Eyal, Gil Shetrit
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Publication number: 20050208735Abstract: The invention is directed to an improvement of cutting accuracy in a cutting process when a semiconductor device attached with a supporting member is manufactured. The invention provides a manufacturing method of a semiconductor device where a semiconductor wafer attached with a glass substrate is cut with moving a rotation blade along a dicing region and has following features. A pair of alignment marks is formed facing each other over the dicing region on the semiconductor wafer. Then, when the rotation blade is to be aligned on a center of the dicing region, that is, on a centerline thereof in the cutting process, positions of the alignment marks are detected by a recognition camera, the centerline is calculated based on the detection result, and the rotation blade is aligned on the centerline to perform cutting.Type: ApplicationFiled: March 2, 2005Publication date: September 22, 2005Applicants: Sanyo Electric Co., Ltd., Kanto SANYO Semiconductors Co., Ltd.Inventors: Takashi Noma, Yoshinori Seki, Motoaki Wakui
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Publication number: 20050048740Abstract: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.Type: ApplicationFiled: August 4, 2004Publication date: March 3, 2005Applicant: Sanyo Electric Co., Ltd.Inventors: Takashi Noma, Katsuhiko Kitagawa, Hisao Otsuka, Akira Suzuki, Yoshinori Seki, Yukihiro Takao, Keiichi Yamaguchi, Motoaki Wakui, Masanori Iida
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Publication number: 20050009302Abstract: The invention provides an algorithm for aligning a rotating blade in a dicing process of partially dicing a wafer attached to a substrate. A width of a cut groove and distance between pads in the cut groove are detected by a recognition camera. Based on a result of this detection, alignment data ?y which is distance between a centerline of the width of the cut groove and a real centerline are calculated. Based on a difference between the distance of the pads in the cut groove and a target value of the distance, data ?z on alignment in a depth direction of the cut groove is calculated. The rotating blade is aligned by using the alignment data ?y and ?z.Type: ApplicationFiled: February 5, 2004Publication date: January 13, 2005Applicant: Sanyo Electric Co., Ltd.Inventors: Motoaki Wakui, Isao Ochiai, Ron Eyal, Gil Shetrit
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Publication number: 20040121562Abstract: A semiconductor device manufacturing method comprises a step of forming a laminated structure by adhering, on a semiconductor substrate including a plurality of integrated circuits, a carrier member covering a region in which the plurality of integrated circuits are formed, with an insulating resin interposed between the semiconductor substrate and the carrier member, a step of cutting a notch into the laminated structure so as to cut the semiconductor substrate together with the insulating resin while allowing at least a portion of the carrier member to remain uncut, and a dicing step for dividing the laminated structure by cutting the carrier member. The notch cutting step is performed while cooling a dicing saw used to cut the semiconductor substrate.Type: ApplicationFiled: November 14, 2003Publication date: June 24, 2004Applicants: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Motoaki Wakui, Kaoru Sasaki, Kenji Imai, Hiroyuki Shinogi, Takashi Noma