Patents by Inventor Motoaki Yasui

Motoaki Yasui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230379383
    Abstract: A communication system includes a first communication apparatus communicating with a processing apparatus and a second communication apparatus performing an obtainment/transmission procedure of obtaining sensor information from a sensor unit and transmitting the sensor information to the first communication apparatus. The sensor unit includes at least one sensor. The first communication apparatus transmits the sensor information from the second communication apparatus to the processing apparatus, in response to an obtainment wish timing with which the processing apparatus wishes to obtain the sensor information. The second communication apparatus determines a start timing to start the obtainment/transmission procedure, based on a first time required to communicate between the first and second communication apparatuses when the second communication apparatus transmits the sensor information to the first communication apparatus.
    Type: Application
    Filed: March 22, 2023
    Publication date: November 23, 2023
    Applicant: MegaChips Corporation
    Inventors: Motoaki YASUI, Hirotaka ONO
  • Patent number: 11709963
    Abstract: A memory system connected to a host computer generating input information, includes a storage configured to store application program executed by the host computer, a contents database relating various contents candidate information used by the host computer with either of plural adjustment candidate identification information, and input information inputted from the host computer, circuitry configured to infer, by executing inference by an artificial intelligence algorithm, specific adjustment candidate identification information as adjustment identification information from the plurality of adjustment candidate identification information according to the input information and select specific contents candidate information as adjustment contents information from the contents database using the adjustment identification information and an interface configured to output the adjustment contents information to the host computer.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: July 25, 2023
    Assignee: MEGACHIPS CORPORATION
    Inventors: Toshio Katsura, Masahiro Shindo, Injie Nakao, Motoaki Yasui, Masashi Kuramoto
  • Publication number: 20200311301
    Abstract: A memory system connected to a host computer generating input information, includes a storage configured to store application program executed by the host computer, a contents database relating various contents candidate information used by the host computer with either of plural adjustment candidate identification information, and input information inputted from the host computer, circuitry configured to infer, by executing inference by an artificial intelligence algorithm, specific adjustment candidate identification information as adjustment identification information from the plurality of adjustment candidate identification information according to the input information and select specific contents candidate information as adjustment contents information from the contents database using the adjustment identification information and an interface configured to output the adjustment contents information to the host computer.
    Type: Application
    Filed: March 27, 2020
    Publication date: October 1, 2020
    Applicant: MegaChips Corporation
    Inventors: Toshio KATSURA, Masahiro SHINDO, Injie NAKAO, Motoaki YASUI, Masashi KURAMOTO
  • Patent number: 9454826
    Abstract: An image processor includes an LSRAM accessible with a higher speed than a frame memory and configured to hold a second image in a predetermined range of a first image, an image production unit configured to read an image in a predetermined range of the second image from the LSRAM and produce a third image for rough search based on the read image, an MSRAM accessible with a higher speed than the frame memory and configured to hold the third image produced by the image production unit, a search unit configured to read the third image from the MSRAM and perform first motion search based on the third image, and a search unit configured to read a fourth image in a predetermined range of the second image from the LSRAM based on a search result by the search unit and perform second motion search that is more detailed than the first motion search based on the fourth image.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: September 27, 2016
    Assignee: MegaChips Corporation
    Inventors: Kazuhiro Saito, Yujiro Tani, Motoaki Yasui
  • Publication number: 20140334688
    Abstract: An image processor includes an LSRAM accessible with a higher speed than a frame memory and configured to hold a second image in a predetermined range of a first image, an image production unit configured to read an image in a predetermined range of the second image from the LSRAM and produce a third image for rough search based on the read image, an MSRAM accessible with a higher speed than the frame memory and configured to hold the third image produced by the image production unit, a search unit configured to read the third image from the MSRAM and perform first motion search based on the third image, and a search unit configured to read a fourth image in a predetermined range of the second image from the LSRAM based on a search result by the search unit and perform second motion search that is more detailed than the first motion search based on the fourth image.
    Type: Application
    Filed: November 30, 2012
    Publication date: November 13, 2014
    Applicant: MegaChips Corporation
    Inventors: Kazuhiro Saito, Yujiro Tani, Motoaki Yasui
  • Publication number: 20130322533
    Abstract: A coding device that achieves reduction in a circuit size and in the number of processing cycles is obtained. A coding device includes a first arithmetic unit that calculates a first difference value between an input image and a predicted image with respect to each of blocks having a first block size included in a macroblock to be coded, and a second arithmetic unit that calculates a second difference value between an input image and a predicted image for each of blocks having a second block size larger than the first block size included in the macroblock, and a prediction mode determination unit that determines a prediction mode to be applied to the macroblock, based on the first difference values of the macroblock calculated by the first arithmetic unit and the second difference values of the macroblock calculated by the second arithmetic unit.
    Type: Application
    Filed: February 21, 2012
    Publication date: December 5, 2013
    Applicant: MEGACHIPS CORPORATION
    Inventors: Motoaki Yasui, Akira Okamoto