Patents by Inventor Motochika Okano

Motochika Okano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150280309
    Abstract: According to one embodiment, an electronic device includes a housing, antenna, and communication module. The housing includes a first region on which an external device is mountable. The first region includes a first side and a second side facing the first side. The antenna is arranged on the first region. The antenna includes at least a first antenna portion and second antenna portion. The first antenna portion is arranged in a first edge region along the first side within the first region. The second antenna portion is arranged in a second edge region along the second side within the first region. The communication module executes a close proximity wireless communication using the antenna.
    Type: Application
    Filed: July 8, 2014
    Publication date: October 1, 2015
    Inventors: Toshiki MIYASAKA, Motochika OKANO
  • Publication number: 20150263416
    Abstract: According to one embodiment, an antenna includes first and second coupling elements and first to fourth connecting elements. An electrical length between a middle point of the first coupling element and each of both open ends thereof is a first electrical length which is an odd multiple of ¼ of a wavelength ? corresponding to a frequency used for close proximity wireless communication. An electrical length between a middle point of the second coupling element and each of both open ends thereof is the first electrical length. An electrical length of each of the first to fourth connecting elements is a second electrical length which is an odd multiple of ¼ of the wavelength ?.
    Type: Application
    Filed: July 1, 2014
    Publication date: September 17, 2015
    Inventors: Motochika Okano, Toshiki Miyasaka
  • Publication number: 20130321238
    Abstract: According to one embodiment, the radio communication apparatus has a printed-wiring board, an electronic element, a first electrode, a second electrode, an antenna, and a molded member. The first electrode is conductor-connected to the printed-wiring board. The second electrode has the same size as the first electrode, is disposed parallel to the first electrode, and capacitively coupled to the first electrode. The molded member buries the printed-wiring board, the electronic element, the first electrode, the second electrode, and the antenna.
    Type: Application
    Filed: February 21, 2013
    Publication date: December 5, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Motochika Okano
  • Patent number: 8146049
    Abstract: According to one embodiment, a design support apparatus determines one of a first impedance between a power plane and a ground plane in the printed circuit board at an ON time of a high-side transistor in the switching power supply, a second impedance between the power plane and the ground plane at an ON time of a low-side transistor in the switching power supply, and a third impedance in an intermediate range between the first impedance and the second impedance to be an impedance between the power plane and the ground plane, based on ON-time information indicative of a ratio of an ON period of the high-side transistor to a switching cycle of the switching power supply in an operation period of the device. The apparatus evaluates capacitor information included in design information of the printed circuit by comparing the determined impedance and a target impedance.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: March 27, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Motochika Okano
  • Publication number: 20110055795
    Abstract: According to one embodiment, a design support apparatus determines one of a first impedance between a power plane and a ground plane in the printed circuit board at an ON time of a high-side transistor in the switching power supply, a second impedance between the power plane and the ground plane at an ON time of a low-side transistor in the switching power supply, and a third impedance in an intermediate range between the first impedance and the second impedance to be an impedance between the power plane and the ground plane, based on ON-time information indicative of a ratio of an ON period of the high-side transistor to a switching cycle of the switching power supply in an operation period of the device. The apparatus evaluates capacitor information included in design information of the printed circuit by comparing the determined impedance and a target impedance.
    Type: Application
    Filed: July 28, 2010
    Publication date: March 3, 2011
    Inventor: Motochika Okano
  • Patent number: 7843703
    Abstract: According to one embodiment, a multilayer printed circuit board having a plurality of wiring layers and an electronic component mounted thereon, includes a spiral wire including a path in a substantial spiral shape configured with a printed wire section of a substantial loop shape provided on each of at least two wiring layers of the plurality of wiring layers, and a plug provided on each wiring layer arranged between a top wiring layer which is a wiring layer on a top on which the printed wire section of a substantial loop shape is provided and a bottom wiring layer which is a wiring layer on a bottom on which the printed wire section of a substantial loop shape is provided.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: November 30, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Motochika Okano
  • Publication number: 20090296362
    Abstract: According to one embodiment, a multilayer printed circuit board having a plurality of wiring layers and an electronic component mounted thereon, includes a spiral wire including a path in a substantial spiral shape configured with a printed wire section of a substantial loop shape provided on each of at least two wiring layers of the plurality of wiring layers, and a plug provided on each wiring layer arranged between a top wiring layer which is a wiring layer on a top on which the printed wire section of a substantial loop shape is provided and a bottom wiring layer which is a wiring layer on a bottom on which the printed wire section of a substantial loop shape is provided.
    Type: Application
    Filed: January 7, 2009
    Publication date: December 3, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Motochika Okano
  • Patent number: 7593213
    Abstract: According to one embodiment, a capacitor arrangement support system includes a resonance analysis module configured to perform a resonance analysis based on data of a component producing electromagnetic radiation, a resonance point extraction module configured to extract a resonance point from an analysis result of the resonance analysis module, an electromagnetically radiated energy analysis module configured to analyze the ease of collection of electromagnetically radiated energy with respect to a resonance point extracted by the resonance point extraction module, a determination module configured to determine whether or not an absolute value of a value showing the ease of collection of electromagnetically radiated energy is larger than a preset absolute value, and a capacitor arrangement module configured to arrange a capacitor for suppressing electromagnetic radiation at a resonance point where the determination module determines that data of the component is larger the preset absolute value.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: September 22, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Motochika Okano
  • Publication number: 20090070724
    Abstract: According to one embodiment, an information processing device includes a registration section for registering terminals of a symbol diagrams to a library by associating a relationship of connections of each of a devices, an extraction section for extracting a hierarchical structure of a power supply system and the symbol diagrams, a connection section for connecting the terminals of the symbol diagrams on the basis of the extracted hierarchical structure of the power supply system and the registered relationship of connections of the symbol diagrams, and a creation section for creating a schematic diagram of a hierarchical structure by connecting the terminals of the symbol diagrams on the basis of the extracted hierarchical structure of the power supply system and the registered relationship of connections of the symbol diagrams.
    Type: Application
    Filed: July 21, 2008
    Publication date: March 12, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Motochika Okano
  • Publication number: 20090059549
    Abstract: According to one embodiment, a capacitor arrangement support system includes a resonance analysis module configured to perform a resonance analysis based on data of a component producing electromagnetic radiation, a resonance point extraction module configured to extract a resonance point from an analysis result of the resonance analysis module, an electromagnetically radiated energy analysis module configured to analyze the ease of collection of electromagnetically radiated energy with respect to a resonance point extracted by the resonance point extraction module, a determination module configured to determine whether or not an absolute value of a value showing the ease of collection of electromagnetically radiated energy is larger than a preset absolute value, and a capacitor arrangement module configured to arrange a capacitor for suppressing electromagnetic radiation at a resonance point where the determination module determines that data of the component is larger the preset absolute value.
    Type: Application
    Filed: July 31, 2008
    Publication date: March 5, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Motochika Okano
  • Patent number: 7418687
    Abstract: An information processing apparatus includes: an input unit; a storing unit configured to store wiring layout information and layer configuration information of a multilayer printed circuit board; a layout displaying unit configured to display a wiring layout drawing based on the wiring layout information; a clipping position specifying unit configured to specify a clipping position on the displayed wiring layout drawing in response to user's operation of the input unit; and a cross section displaying unit configured to display a cross section indicating a cross-sectional structure of the wiring layout of the multilayer printed circuit board along the specified clipping position on the display based on the wiring layout information and the layer configuration information.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: August 26, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Motochika Okano, Kazushi Ikeda
  • Patent number: 7257793
    Abstract: An information display method includes converting circuit diagram CAD data of a circuit board into a first standard format and converting layout diagram CAD data of the circuit board into a second standard format, displaying a circuit diagram based on the circuit diagram CAD data converted into the first standard format on a screen of a circuit-diagram viewer and displaying a layout diagram based on the layout diagram CAD data converted into the second standard format on a screen of a layout-diagram viewer, highlighting a circuit element selected on the screen of either the circuit-diagram viewer or the layout-diagram viewer using specified color, and giving information for identifying the circuit element selected on the screen to another viewer, and highlighting an element corresponding to the circuit element identified by the given information on the screen of the viewer receiving the information using specified color.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: August 14, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Motochika Okano, Kazushi Ikeda, Kazuyuki Matsuda
  • Publication number: 20060002215
    Abstract: An information processing apparatus includes: an input unit; a storing unit configured to store wiring layout information and layer configuration information of a multilayer printed circuit board; a layout displaying unit configured to display a wiring layout drawing based on the wiring layout information; a clipping position specifying unit configured to specify a clipping position on the displayed wiring layout drawing in response to user's operation of the input unit; and a cross section displaying unit configured to display a cross section indicating a cross-sectional structure of the wiring layout of the multilayer printed circuit board along the specified clipping position on the display based on the wiring layout information and the layer configuration information.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 5, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Motochika Okano, Kazushi Ikeda
  • Publication number: 20050091626
    Abstract: An information display method includes converting circuit diagram CAD data of a circuit board into a first standard format and converting layout diagram CAD data of the circuit board into a second standard format, displaying a circuit diagram based on the circuit diagram CAD data converted into the first standard format on a screen of a circuit-diagram viewer and displaying a layout diagram based on the layout diagram CAD data converted into the second standard format on a screen of a layout-diagram viewer, highlighting a circuit element selected on the screen of either the circuit-diagram viewer or the layout-diagram viewer using specified color, and giving information for identifying the circuit element selected on the screen to another viewer, and highlighting an element corresponding to the circuit element identified by the given information on the screen of the viewer receiving the information using specified color.
    Type: Application
    Filed: September 24, 2004
    Publication date: April 28, 2005
    Inventors: Motochika Okano, Kazushi Ikeda, Kazuyuki Matsuda