Abstract: Provided are a system, method, and device for intelligent test environment allocation. According to embodiments, the method for intelligently determining one or more test environments for testing software of an embedded system, may include: obtaining, by a task allocator, capability information of a plurality of test environments; obtaining, by the task allocator, policy information of a task to be executed for testing the software of the embedded system; determining, by the task allocator, a test environment, from among the plurality of test environments, that satisfies the policy information; and allocating, by the task allocator, the task to the determined test environment, wherein the embedded system may be an in-vehicle electronic control unit (ECU), and wherein the plurality of tests environments may include at least one software-in-the-loop (SIL) test environment, at least one hardware-in-the-loop (HIL) test environment, and at least one virtual ECU (V-ECU) test environment.

Abstract: An integrated device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access. An input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros. As connection interconnects, command information interconnects and data interconnects are included. The command information interconnects are formed by private interconnects, while the data interconnects are formed by private interconnects for at least the second direction interconnects.

Abstract: A shared memory device is disclosed which includes: a plurality of processor elements; a plurality of memory modules configured to be accessible by the plurality of processor elements; and a connection device configured to enable a specific processor element out of the plurality of processor elements to access a specific memory module out of the plurality of memory modules; wherein the plurality of processor elements are allowed to access via the connection device a plurality of memory systems each constituted by at least one memory module; and wherein each of the plurality of memory systems accessible by different processor elements allows the plurality of memory modules to be partially shared and accessed by the different processor elements.

Abstract: History memory 430 correlates the input values and execution result of a function for each piece of function identification information, and holds as an execution history. A command decoder 320 supplies function identification information included in a previous notice command for predicting the function from a fetch unit 310 to an execution history search unit 410. Also, the command decoder 320 causes the execution history search unit 410 to obtain the input value output from an input selecting unit 332 based on, of commands to be read out after the previous notice command, an input value setting command for setting a function input value. The execution history search unit 410 searches an execution history agreeing with the obtained identification information and input values thereof before a function call-up command. An execution result output unit 420 outputs the execution result detected by the execution history search unit 410 to an executing unit 330.

Abstract: An integrated device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access. An input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros. As connection interconnects, command information interconnects and data interconnects are included. The command information interconnects are formed by private interconnects, while the data interconnects are formed by private interconnects for at least the second direction interconnects.

Abstract: An integrated device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access. An input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros. As connection interconnects, command information interconnects and data interconnects are included. The command information interconnects are formed by private interconnects, while the data interconnects are formed by private interconnects for at least the second direction interconnects.

Abstract: A shared memory device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access, wherein an input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros.

Abstract: A shared memory device is disclosed which includes: a plurality of processor elements; a plurality of memory modules configured to be accessible by the plurality of processor elements; and a connection device configured to enable a specific processor element out of the plurality of processor elements to access a specific memory module out of the plurality of memory modules; wherein the plurality of processor elements are allowed to access via the connection device a plurality of memory systems each constituted by at least one memory module; and wherein each of the plurality of memory systems accessible by different processor elements allows the plurality of memory modules to be partially shared and accessed by the different processor elements.

Abstract: A shared memory device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access, wherein an input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros.

Abstract: An integrated device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access. An input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros. As connection interconnects, command information interconnects and data interconnects are included. The command information interconnects are formed by private interconnects, while the data interconnects are formed by private interconnects for at least the second direction interconnects.

Abstract: A nonvolatile memory producing apparatus has a data computing section 31, an electron patterning section 33 for patterning a wafer 3 by using an electron beam, a control section 32 for controlling +the electron patterning section 33 on the basis of the result from the data computing section 31. The data computing section 31 prepares binary codes for individual IC chips formed on the wafer 3, and generates coordinate regarding the wafer 3 and the IC chips. The data computing section 31 computes direct draw data for each IC chip based on the binary codes, and generates direct pattern data based on the binary codes and the direct draw data. The control section 32 and the electron-beam patterning section 33 cooperate to perform direct electron-beam patterning on the IC chips in accordance with the pattern data.