Patents by Inventor Motofumi Saitoh
Motofumi Saitoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240087840Abstract: An electron microscope includes an irradiation optical system that irradiates a specimen with an electron beam, a specimen stage that supports the specimen, an image forming optical system that forms an image of electrons transmitted through the specimen, an imaging apparatus that captures an image formed by the image forming optical system, and a control unit that controls inclination of the specimen with respect to an incident direction of the electron beam. The irradiation optical system includes an aperture that cuts off a part of the electron beam to be irradiated to the specimen. The control unit acquires an image including Kikuchi bands that appear in a shadow region of the aperture, detects the Kikuchi bands in the shadow region of the aperture in the image, and controls inclination of the specimen with respect to the incident direction of the electron beam, based on the detected Kikuchi bands.Type: ApplicationFiled: September 7, 2023Publication date: March 14, 2024Inventors: Motofumi Saitoh, Shuji Kawai
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Patent number: 10056144Abstract: According to one embodiment, an operation program of a nonvolatile semiconductor memory device includes: a first step for determining whether data has been sufficiently written to all of a plurality of addresses to which data is to be written; and a second step for writing data to an address to which data has not been sufficiently written among the plurality of addresses to which data is to be written and not writing data to an address to which data has been sufficiently written. The first step and the second step are repeated a predetermined number of times.Type: GrantFiled: April 22, 2016Date of Patent: August 21, 2018Assignee: Renesas Electronics CorporationInventor: Motofumi Saitoh
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Publication number: 20160379711Abstract: According to one embodiment, an operation program of a nonvolatile semiconductor memory device includes: a first step for determining whether data has been sufficiently written to all of a plurality of addresses to which data is to be written; and a second step for writing data to an address to which data has not been sufficiently written among the plurality of addresses to which data is to be written and not writing data to an address to which data has been sufficiently written. The first step and the second step are repeated a predetermined number of times.Type: ApplicationFiled: April 22, 2016Publication date: December 29, 2016Applicant: Renesas Electronics CorporationInventor: Motofumi SAITOH
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Patent number: 9362110Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four ? atoms and hexa-coordinated Al atoms each surrounded by six ? atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.Type: GrantFiled: August 23, 2014Date of Patent: June 7, 2016Assignee: Renesas Electronics CorporationInventors: Nobuyuki Ikarashi, Takashi Onizawa, Motofumi Saitoh
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Patent number: 9002144Abstract: A downsized, low-power electro-optical modulator that achieves reducing both of the additional resistance in the modulation portion and the optical loss each caused by electrodes at the same time is provided. The electro-optical modulator includes a rib waveguide formed by stacking a second semiconductor layer 9 having a different conductivity type from a first semiconductor layer 8 on the first semiconductor layer 8 via a dielectric film 11, and the semiconductor layers 8 and 9 are connectable to an external terminal via highly-doped portions 4 and 10, respectively. In a region in the vicinity of contact surfaces of the semiconductor layers 8 and 9 with the dielectric film 11, a free carrier is accumulated, removed, or inverted by an electrical signal from the external terminal, and whereby a concentration of the free carrier in an electric field region of an optical signal is modulated, so that a phase of the optical signal can be modulated.Type: GrantFiled: June 8, 2010Date of Patent: April 7, 2015Assignee: NEC CorporationInventors: Junichi Fujikata, Jun Ushida, Akio Toda, Motofumi Saitoh
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Publication number: 20140363982Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four ? atoms and hexa-coordinated Al atoms each surrounded by six ? atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.Type: ApplicationFiled: August 23, 2014Publication date: December 11, 2014Inventors: Nobuyuki Ikarashi, Takashi Onizawa, Motofumi Saitoh
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Patent number: 8872234Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four O atoms and hexa-coordinated Al atoms each surrounded by six O atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.Type: GrantFiled: January 4, 2013Date of Patent: October 28, 2014Assignee: Renesas Electronics CorporationInventors: Nobuyuki Ikarashi, Takashi Onizawa, Motofumi Saitoh
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Patent number: 8873895Abstract: To provide an optical modulator having a reduced size and reduced power consumption and capable of being easily connected to a waveguide and a method of manufacturing the optical modulator. The optical modulator has at least semiconductor layer (8) having a rib-shaped portion and doped so as to be of a first conduction type, dielectric layer (11) laid on first-conduction-type semiconductor layer (8), and semiconductor layer (9) laid on dielectric layer (11), having the width at the side opposite from dielectric layer (11) increased relative to the width of the rib-shaped portion, and doped so as to be of a second conduction type.Type: GrantFiled: March 1, 2011Date of Patent: October 28, 2014Assignee: NEC CorporationInventors: Junichi Fujikata, Motofumi Saitoh, Jun Ushida, Akio Toda
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Patent number: 8787067Abstract: Provided is a semiconductor device including: a memory cell having a variable resistance device; and a control unit that controls a voltage applied to the memory cell, wherein the variable resistance device includes a lower electrode contains a first metal material, an upper electrode containing a second metal material, and an insulating film containing oxygen, the first metal material has a normalized oxide formation energy higher than that of the second metal material, and the control unit applies a positive voltage to the upper electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applies a positive voltage to the lower electrode at the time of an operation of reading out the resistance value of the insulating film.Type: GrantFiled: January 26, 2012Date of Patent: July 22, 2014Assignee: Renesas Electronics CorporationInventors: Motofumi Saitoh, Masayuki Terai
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Patent number: 8483520Abstract: An optical modulation structure includes a lower cladding layer (102), a first silicon layer (103) integrally formed from silicon of a first conductivity type on the lower cladding layer (102) while including a core (104) and slab regions (105) arranged on both sides of the core (104) and connected to the core, a concave portion (104a) formed in an upper surface of the core (104), and a second silicon layer (109) of a second conductivity type formed on a dielectric layer (108) in the concave portion (104a) so as to fill the concave portion (104a).Type: GrantFiled: February 18, 2010Date of Patent: July 9, 2013Assignee: NEC CorporationInventors: Junichi Fujikata, Jun Ushida, Akio Toda, Motofumi Saitoh
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Publication number: 20130064491Abstract: To provide an optical modulator having a reduced size and reduced power consumption and capable of being easily connected to a waveguide and a method of manufacturing the optical modulator. The optical modulator has at least semiconductor layer (8) having a rib-shaped portion and doped so as to be of a first conduction type, dielectric layer (11) laid on first-conduction-type semiconductor layer (8), and semiconductor layer (9) laid on dielectric layer (11), having the width at the side opposite from dielectric layer (11) increased relative to the width of the rib-shaped portion, and doped so as to be of a second conduction type.Type: ApplicationFiled: March 1, 2011Publication date: March 14, 2013Applicant: NEC CORPORATIONInventors: Junichi Fujikata, Motofumi Saitoh, Jun Ushida, Akio Toda
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Publication number: 20120257850Abstract: A downsized, low-power electro-optical modulator that achieves reducing both of the additional resistance in the modulation portion and the optical loss each caused by electrodes at the same time is provided. The electro-optical modulator includes a rib waveguide formed by stacking a second semiconductor layer 9 having a different conductivity type from a first semiconductor layer 8 on the first semiconductor layer 8 via a dielectric film 11, and the semiconductor layers 8 and 9 are connectable to an external terminal via highly-doped portions 4 and 10, respectively. In a region in the vicinity of contact surfaces of the semiconductor layers 8 and 9 with the dielectric film 11, a free carrier is accumulated, removed, or inverted by an electrical signal from the external terminal, and whereby a concentration of the free carrier in an electric field region of an optical signal is modulated, so that a phase of the optical signal can be modulated.Type: ApplicationFiled: June 8, 2010Publication date: October 11, 2012Applicant: NEC CORPORATIONInventors: Junichi Fujikata, Jun Ushida, Akio Toda, Motofumi Saitoh
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Publication number: 20120195100Abstract: Provided is a semiconductor device including: a memory cell having a variable resistance device; and a control unit that controls a voltage applied to the memory cell, wherein the variable resistance device includes a lower electrode contains a first metal material, an upper electrode containing a second metal material, and an insulating film containing oxygen, the first metal material has a normalized oxide formation energy higher than that of the second metal material, and the control unit applies a positive voltage to the upper electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applies a positive voltage to the lower electrode at the time of an operation of reading out the resistance value of the insulating film.Type: ApplicationFiled: January 26, 2012Publication date: August 2, 2012Applicant: Renesas Electronics CorporationInventors: Motofumi SAITOH, Masayuki Terai
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Publication number: 20120104614Abstract: A semiconductor device manufacturing method which prevents the resistance of a Ni silicide layer from increasing due to an additive element. First, a reaction control layer which contains a metallic element with an atomic number greater than Ni and does not contain Ni is formed over a silicon layer. Then, Ni is deposited over the reaction control layer and the silicon layer, reaction control layer and Ni are heat-treated to form a Ni silicide layer in the silicon layer. It is preferable that the reaction control layer be comprised of a metallic element with an atomic number greater than Ni.Type: ApplicationFiled: October 21, 2011Publication date: May 3, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Nobuyuki IKARASHI, Motofumi SAITOH, Kouji MASUZAKI
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Publication number: 20110311178Abstract: The components are a lower clad layer (102), a first silicon layer (103) that is formed on the lower clad layer (102) as a single body made of silicon of a first conduction type and has a slab region (105) that is disposed at a core (104) and on both sides of the core (104) and connects to the core, a concave section (104a) that is formed in the top surface of the core (104), and a second silicon layer (109) of a second conduction type that is formed inside the concave section (104a) with an intervening dielectric layer (108) to fill the inside of the concave section (104a).Type: ApplicationFiled: February 18, 2010Publication date: December 22, 2011Applicant: NEC CORPORATIONInventors: Junichi Fujikata, Jun Ushida, Akio Toda, Motofumi Saitoh
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Patent number: 7838945Abstract: A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first and second active regions, respectively, a gate electrode composed of the line-shaped electrode and a source/drain region. Parts of the line-shaped electrode over the first and second active regions are formed of different materials. The line-shaped electrode includes a diffusion restraining region having thickness in a direction perpendicular to the substrate thinner than that over the first and second active regions. The diffusion restraining region is over the element isolation region and spans the whole width of the line-shaped electrode in the gate length direction.Type: GrantFiled: October 18, 2006Date of Patent: November 23, 2010Assignee: NEC CorporationInventors: Motofumi Saitoh, Hirohito Watanabe
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Patent number: 7759744Abstract: A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 12 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from Hf and Zr.Type: GrantFiled: May 16, 2005Date of Patent: July 20, 2010Assignees: NEC Electronics Corporation, NEC CorporationInventors: Naohiko Kimizuka, Kiyotaka Imai, Yuri Masuoka, Toshiyuki Iwamoto, Motofumi Saitoh, Hirohito Watanabe, Masayuki Terai
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Publication number: 20090096032Abstract: A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first and second active regions, respectively, a gate electrode composed of the line-shaped electrode and a source/drain region. Parts of the line-shaped electrode over the first and second active regions are formed of different materials. The line-shaped electrode includes a diffusion restraining region having thickness in a direction perpendicular to the substrate thinner than that over the first and second active regions. The diffusion restraining region is over the element isolation region and spans the whole width of the line-shaped electrode in the gate length direction.Type: ApplicationFiled: October 18, 2006Publication date: April 16, 2009Applicant: NEC CORPORATIONInventors: Motofumi Saitoh, Hirohito Watanabe
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Patent number: 7238996Abstract: A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.Type: GrantFiled: May 16, 2005Date of Patent: July 3, 2007Assignees: NEC Electronics Corporation, NEC CorporationInventors: Naohiko Kimizuka, Kiyotaka Imai, Yuri Masuoka, Toshiyuki Iwamoto, Motofumi Saitoh, Hirohito Watanabe, Ayuka Tada
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Publication number: 20050263802Abstract: A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.Type: ApplicationFiled: May 16, 2005Publication date: December 1, 2005Applicants: NEC ELECTRONICS CORPORATION, NEC CORPORATIONInventors: Naohiko Kimizuka, Kiyotaka Imai, Yuri Masuoka, Toshiyuki Iwamoto, Motofumi Saitoh, Hirohito Watanabe, Ayuka Tada