Patents by Inventor Motofumi Saitoh

Motofumi Saitoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240087840
    Abstract: An electron microscope includes an irradiation optical system that irradiates a specimen with an electron beam, a specimen stage that supports the specimen, an image forming optical system that forms an image of electrons transmitted through the specimen, an imaging apparatus that captures an image formed by the image forming optical system, and a control unit that controls inclination of the specimen with respect to an incident direction of the electron beam. The irradiation optical system includes an aperture that cuts off a part of the electron beam to be irradiated to the specimen. The control unit acquires an image including Kikuchi bands that appear in a shadow region of the aperture, detects the Kikuchi bands in the shadow region of the aperture in the image, and controls inclination of the specimen with respect to the incident direction of the electron beam, based on the detected Kikuchi bands.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 14, 2024
    Inventors: Motofumi Saitoh, Shuji Kawai
  • Patent number: 10056144
    Abstract: According to one embodiment, an operation program of a nonvolatile semiconductor memory device includes: a first step for determining whether data has been sufficiently written to all of a plurality of addresses to which data is to be written; and a second step for writing data to an address to which data has not been sufficiently written among the plurality of addresses to which data is to be written and not writing data to an address to which data has been sufficiently written. The first step and the second step are repeated a predetermined number of times.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: August 21, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Motofumi Saitoh
  • Publication number: 20160379711
    Abstract: According to one embodiment, an operation program of a nonvolatile semiconductor memory device includes: a first step for determining whether data has been sufficiently written to all of a plurality of addresses to which data is to be written; and a second step for writing data to an address to which data has not been sufficiently written among the plurality of addresses to which data is to be written and not writing data to an address to which data has been sufficiently written. The first step and the second step are repeated a predetermined number of times.
    Type: Application
    Filed: April 22, 2016
    Publication date: December 29, 2016
    Applicant: Renesas Electronics Corporation
    Inventor: Motofumi SAITOH
  • Patent number: 9362110
    Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four ? atoms and hexa-coordinated Al atoms each surrounded by six ? atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.
    Type: Grant
    Filed: August 23, 2014
    Date of Patent: June 7, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Ikarashi, Takashi Onizawa, Motofumi Saitoh
  • Patent number: 9002144
    Abstract: A downsized, low-power electro-optical modulator that achieves reducing both of the additional resistance in the modulation portion and the optical loss each caused by electrodes at the same time is provided. The electro-optical modulator includes a rib waveguide formed by stacking a second semiconductor layer 9 having a different conductivity type from a first semiconductor layer 8 on the first semiconductor layer 8 via a dielectric film 11, and the semiconductor layers 8 and 9 are connectable to an external terminal via highly-doped portions 4 and 10, respectively. In a region in the vicinity of contact surfaces of the semiconductor layers 8 and 9 with the dielectric film 11, a free carrier is accumulated, removed, or inverted by an electrical signal from the external terminal, and whereby a concentration of the free carrier in an electric field region of an optical signal is modulated, so that a phase of the optical signal can be modulated.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: April 7, 2015
    Assignee: NEC Corporation
    Inventors: Junichi Fujikata, Jun Ushida, Akio Toda, Motofumi Saitoh
  • Publication number: 20140363982
    Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four ? atoms and hexa-coordinated Al atoms each surrounded by six ? atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.
    Type: Application
    Filed: August 23, 2014
    Publication date: December 11, 2014
    Inventors: Nobuyuki Ikarashi, Takashi Onizawa, Motofumi Saitoh
  • Patent number: 8872234
    Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four O atoms and hexa-coordinated Al atoms each surrounded by six O atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: October 28, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Ikarashi, Takashi Onizawa, Motofumi Saitoh
  • Patent number: 8873895
    Abstract: To provide an optical modulator having a reduced size and reduced power consumption and capable of being easily connected to a waveguide and a method of manufacturing the optical modulator. The optical modulator has at least semiconductor layer (8) having a rib-shaped portion and doped so as to be of a first conduction type, dielectric layer (11) laid on first-conduction-type semiconductor layer (8), and semiconductor layer (9) laid on dielectric layer (11), having the width at the side opposite from dielectric layer (11) increased relative to the width of the rib-shaped portion, and doped so as to be of a second conduction type.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: October 28, 2014
    Assignee: NEC Corporation
    Inventors: Junichi Fujikata, Motofumi Saitoh, Jun Ushida, Akio Toda
  • Patent number: 8787067
    Abstract: Provided is a semiconductor device including: a memory cell having a variable resistance device; and a control unit that controls a voltage applied to the memory cell, wherein the variable resistance device includes a lower electrode contains a first metal material, an upper electrode containing a second metal material, and an insulating film containing oxygen, the first metal material has a normalized oxide formation energy higher than that of the second metal material, and the control unit applies a positive voltage to the upper electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applies a positive voltage to the lower electrode at the time of an operation of reading out the resistance value of the insulating film.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: July 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Motofumi Saitoh, Masayuki Terai
  • Patent number: 8483520
    Abstract: An optical modulation structure includes a lower cladding layer (102), a first silicon layer (103) integrally formed from silicon of a first conductivity type on the lower cladding layer (102) while including a core (104) and slab regions (105) arranged on both sides of the core (104) and connected to the core, a concave portion (104a) formed in an upper surface of the core (104), and a second silicon layer (109) of a second conductivity type formed on a dielectric layer (108) in the concave portion (104a) so as to fill the concave portion (104a).
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: July 9, 2013
    Assignee: NEC Corporation
    Inventors: Junichi Fujikata, Jun Ushida, Akio Toda, Motofumi Saitoh
  • Publication number: 20130064491
    Abstract: To provide an optical modulator having a reduced size and reduced power consumption and capable of being easily connected to a waveguide and a method of manufacturing the optical modulator. The optical modulator has at least semiconductor layer (8) having a rib-shaped portion and doped so as to be of a first conduction type, dielectric layer (11) laid on first-conduction-type semiconductor layer (8), and semiconductor layer (9) laid on dielectric layer (11), having the width at the side opposite from dielectric layer (11) increased relative to the width of the rib-shaped portion, and doped so as to be of a second conduction type.
    Type: Application
    Filed: March 1, 2011
    Publication date: March 14, 2013
    Applicant: NEC CORPORATION
    Inventors: Junichi Fujikata, Motofumi Saitoh, Jun Ushida, Akio Toda
  • Publication number: 20120257850
    Abstract: A downsized, low-power electro-optical modulator that achieves reducing both of the additional resistance in the modulation portion and the optical loss each caused by electrodes at the same time is provided. The electro-optical modulator includes a rib waveguide formed by stacking a second semiconductor layer 9 having a different conductivity type from a first semiconductor layer 8 on the first semiconductor layer 8 via a dielectric film 11, and the semiconductor layers 8 and 9 are connectable to an external terminal via highly-doped portions 4 and 10, respectively. In a region in the vicinity of contact surfaces of the semiconductor layers 8 and 9 with the dielectric film 11, a free carrier is accumulated, removed, or inverted by an electrical signal from the external terminal, and whereby a concentration of the free carrier in an electric field region of an optical signal is modulated, so that a phase of the optical signal can be modulated.
    Type: Application
    Filed: June 8, 2010
    Publication date: October 11, 2012
    Applicant: NEC CORPORATION
    Inventors: Junichi Fujikata, Jun Ushida, Akio Toda, Motofumi Saitoh
  • Publication number: 20120195100
    Abstract: Provided is a semiconductor device including: a memory cell having a variable resistance device; and a control unit that controls a voltage applied to the memory cell, wherein the variable resistance device includes a lower electrode contains a first metal material, an upper electrode containing a second metal material, and an insulating film containing oxygen, the first metal material has a normalized oxide formation energy higher than that of the second metal material, and the control unit applies a positive voltage to the upper electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applies a positive voltage to the lower electrode at the time of an operation of reading out the resistance value of the insulating film.
    Type: Application
    Filed: January 26, 2012
    Publication date: August 2, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Motofumi SAITOH, Masayuki Terai
  • Publication number: 20120104614
    Abstract: A semiconductor device manufacturing method which prevents the resistance of a Ni silicide layer from increasing due to an additive element. First, a reaction control layer which contains a metallic element with an atomic number greater than Ni and does not contain Ni is formed over a silicon layer. Then, Ni is deposited over the reaction control layer and the silicon layer, reaction control layer and Ni are heat-treated to form a Ni silicide layer in the silicon layer. It is preferable that the reaction control layer be comprised of a metallic element with an atomic number greater than Ni.
    Type: Application
    Filed: October 21, 2011
    Publication date: May 3, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Nobuyuki IKARASHI, Motofumi SAITOH, Kouji MASUZAKI
  • Publication number: 20110311178
    Abstract: The components are a lower clad layer (102), a first silicon layer (103) that is formed on the lower clad layer (102) as a single body made of silicon of a first conduction type and has a slab region (105) that is disposed at a core (104) and on both sides of the core (104) and connects to the core, a concave section (104a) that is formed in the top surface of the core (104), and a second silicon layer (109) of a second conduction type that is formed inside the concave section (104a) with an intervening dielectric layer (108) to fill the inside of the concave section (104a).
    Type: Application
    Filed: February 18, 2010
    Publication date: December 22, 2011
    Applicant: NEC CORPORATION
    Inventors: Junichi Fujikata, Jun Ushida, Akio Toda, Motofumi Saitoh
  • Patent number: 7838945
    Abstract: A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first and second active regions, respectively, a gate electrode composed of the line-shaped electrode and a source/drain region. Parts of the line-shaped electrode over the first and second active regions are formed of different materials. The line-shaped electrode includes a diffusion restraining region having thickness in a direction perpendicular to the substrate thinner than that over the first and second active regions. The diffusion restraining region is over the element isolation region and spans the whole width of the line-shaped electrode in the gate length direction.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: November 23, 2010
    Assignee: NEC Corporation
    Inventors: Motofumi Saitoh, Hirohito Watanabe
  • Patent number: 7759744
    Abstract: A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 12 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from Hf and Zr.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: July 20, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Naohiko Kimizuka, Kiyotaka Imai, Yuri Masuoka, Toshiyuki Iwamoto, Motofumi Saitoh, Hirohito Watanabe, Masayuki Terai
  • Publication number: 20090096032
    Abstract: A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first and second active regions, respectively, a gate electrode composed of the line-shaped electrode and a source/drain region. Parts of the line-shaped electrode over the first and second active regions are formed of different materials. The line-shaped electrode includes a diffusion restraining region having thickness in a direction perpendicular to the substrate thinner than that over the first and second active regions. The diffusion restraining region is over the element isolation region and spans the whole width of the line-shaped electrode in the gate length direction.
    Type: Application
    Filed: October 18, 2006
    Publication date: April 16, 2009
    Applicant: NEC CORPORATION
    Inventors: Motofumi Saitoh, Hirohito Watanabe
  • Patent number: 7238996
    Abstract: A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: July 3, 2007
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Naohiko Kimizuka, Kiyotaka Imai, Yuri Masuoka, Toshiyuki Iwamoto, Motofumi Saitoh, Hirohito Watanabe, Ayuka Tada
  • Publication number: 20050263802
    Abstract: A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.
    Type: Application
    Filed: May 16, 2005
    Publication date: December 1, 2005
    Applicants: NEC ELECTRONICS CORPORATION, NEC CORPORATION
    Inventors: Naohiko Kimizuka, Kiyotaka Imai, Yuri Masuoka, Toshiyuki Iwamoto, Motofumi Saitoh, Hirohito Watanabe, Ayuka Tada