Patents by Inventor Motoharu Ishii
Motoharu Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7791943Abstract: In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.Type: GrantFiled: October 1, 2009Date of Patent: September 7, 2010Assignee: Renesas Technology Corp.Inventors: Motoharu Ishii, Seiichi Endo
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Publication number: 20100014355Abstract: In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.Type: ApplicationFiled: October 1, 2009Publication date: January 21, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Motoharu Ishii, Seiichi Endo
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Publication number: 20080144383Abstract: In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.Type: ApplicationFiled: January 18, 2008Publication date: June 19, 2008Applicant: Renesas Technology Corp.Inventors: Motoharu Ishii, Seiichi Endo
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Publication number: 20080099825Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate having a principal surface, memory transistors, and selection transistors. Each of the memory transistors has a floating gate and a control gate that are formed by lamination with each other on the principal surface. Each of the selection transistors has a lower gate layer and an upper gate layer that are formed by lamination with each other on the principal surface, and is contained in a memory cell together with one of the memory transistors. The lower gate layer is separated for each one of the selection transistors. The upper gate layer is owned commonly by the selection transistors and is electrically connected to the lower gate layer of each of the selection transistors. Therefore, it is possible to prevent short-circuiting of the selection transistors and the memory transistors.Type: ApplicationFiled: October 25, 2007Publication date: May 1, 2008Inventors: Motoharu Ishii, Kiyohiko Sakakibara
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Patent number: 7342828Abstract: In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.Type: GrantFiled: April 27, 2006Date of Patent: March 11, 2008Assignee: Renesas Technology Corp.Inventors: Motoharu Ishii, Seiichi Endo
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Publication number: 20060245254Abstract: In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.Type: ApplicationFiled: April 27, 2006Publication date: November 2, 2006Inventors: Motoharu Ishii, Seiichi Endo
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Publication number: 20050012138Abstract: A nonvolatile semiconductor memory device includes: a semiconductor substrate having a main surface; a pair of p-type impurity diffused regions, formed at the main surface of the semiconductor substrate to serve as source/drain; a floating gate formed on a region of the semiconductor substrate lying between the paired p-type impurity diffused regions, with a tunnel insulating layer interposed between the floating gate and the region of the semiconductor substrate; and an impurity diffused control region formed at the main surface of the semiconductor substrate to control a potential of the floating gate. Accordingly, a nonvolatile semiconductor device can be obtained in which data can be electrically erased and written at a low voltage.Type: ApplicationFiled: January 15, 2004Publication date: January 20, 2005Inventors: Seiichi Endo, Motoharu Ishii
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Publication number: 20030057510Abstract: A gate insulation film is provided on the surface of silicon substrate, a first gate electrode is provided on the gate insulation film, an interlayer insulation film is provided on the first gate electrode, a second gate electrode is provided on the interlayer insulation film, and the first gate electrode is fixed at a reference potential. Subsequently, a predetermined voltage is applied to the part of the substrate opposed to the first and second gate electrodes.Type: ApplicationFiled: August 12, 2002Publication date: March 27, 2003Inventor: Motoharu Ishii
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Patent number: 6538930Abstract: A charge pump circuit comprising: a first reverse current prevention circuit connected between an external power supply and a first internal node; a first output node, connected to the first internal node, for outputting a first output potential; a second reverse current prevention circuit connected between a second power supply node receiving ground potential and a second internal node; and power supply generation circuit, connected between the first internal node and second internal node, for enhancing the potential of the second internal node as compared to that of the first internal node, wherein the power supply generation circuit is formed on or within a semiconductor substrate, and includes a diode element provided so as to flow a current from the first internal node to the second internal node, and a capacitor having one electrode connected to the first and second nodes, and the other electrode provided with a clock signal, thereby enabling higher outputs on both positive and negative voltages.Type: GrantFiled: October 10, 2001Date of Patent: March 25, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Motoharu Ishii, Kayoko Omoto
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Publication number: 20020089889Abstract: There is a provided a charge pump circuit comprising: a first reverse current prevention circuit connected between an external power supply and a first internal node; a first output node, connected to the first internal node, for outputting a first output potential; a second reverse current prevention circuit connected between a second power supply node receiving ground potential and a second internal node; power supply node for receiving a first power supply potential; a first reverse current prevention means connected between the first power supply node and a first internal node; a first output node, connected to the first internal node, for outputting a first output potential; and power supply generation means, connected between the first internal node and second internal node, for enhancing the potential of the second internal node as compared to that of the first internal node, wherein the power supply generation means is formed on or within a semiconductor substrate, and includes a diode element provideType: ApplicationFiled: October 10, 2001Publication date: July 11, 2002Inventors: Motoharu Ishii, Kayoko Omoto
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Patent number: 6069518Abstract: In response to complementary clock signals provided from a driver, a charge pump operates to provide an output voltage which is a down-converted negative voltage. The voltage between this output voltage and a predetermined positive reference voltage is capacitance-divided by capacitors. The capacitance-divided positive voltage is applied to a comparator, whereby a reference voltage is compared with the above positive voltage. An output signal of the comparator is applied to the driver. In response, the driver controls the operation of the charge pump, whereby the output voltage is clamped at a predetermined voltage level for output.Type: GrantFiled: December 1, 1994Date of Patent: May 30, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroaki Nakai, Shinichi Kobayashi, Motoharu Ishii, Atsushi Ohba, Tomoshi Futatsuya, Akira Hosogane
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Patent number: 5896317Abstract: It is assumed that, in each memory cell array, a first bit line corresponds to a selected address. In this case, a potential on only the first bit line attains H-level. Data to be loaded is supplied to a latch circuit corresponding to the first bit line through a data line arranged independently of the bit line. All the bit lines are reset upon every completion of loading of data of 1 byte. Therefore, rapid data reading can be performed even when data is to be read from a memory cell array immediately after the data is loaded into a latch circuit, or destruction of data already loaded into the latch circuit can be prevented. Further, a circuit area can be reduced.Type: GrantFiled: May 7, 1997Date of Patent: April 20, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Motoharu Ishii, Shinichi Kobayashi, Akinori Matsuo, Masashi Wada
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Patent number: 5521864Abstract: A bit line reset transistor resets every second bit line of a plurality of bit lines to be write-verified. At this time, a transfer gate disconnects a column latch from the unreset bit line. Then, the unreset bit line is precharged in accordance with data of the column latch, while applying a verify voltage to a word line. Then, a source line transistor grounds a source line, and the bit line is connected to the column latch, so that data corresponding to a value of a threshold voltage of the memory cell is held by the column latch, and a write verifying operation is performed.Type: GrantFiled: February 9, 1995Date of Patent: May 28, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shinichi Kobayashi, Hiroaki Nakai, Motoharu Ishii, Atsushi Ohba, Tomoshi Futatsuya, Akira Hosogane