Abstract: The inter-module communication apparatus includes a first module and a second module which operate individually on a processor; a common memory interposed between the first module and the second module for functioning as a communication medium; a plurality of communication paths provided to the common memory for connecting the first module and the second module to be communicable; a transmission unit for transmitting communication data from the first module to the second module; a reception unit for receiving the communication data transmitted from the first module by the second module; a processing order relating device for registering a processing order of communication processing, which is set between each communication path constituting a plurality of the communication paths; and a processing order relevance register which, for transmission, registers the processing order to the processing order relating device when the processing order is set for the communication data to be transmitted.

Abstract: A data communication device is provided wherein a data storage region and a process request region indicative of whether or not there is a process request of data transmission are secured on a memory. A data transmission section receives a request for data transmission from a transmission module to store data in the data storage region and, only when a process request is not yet written in the process request region, writes a process request in the process request region to issue an interrupt to a process request receiving section. The process request receiving section confirms that a process request is written in the process request region and clears the process request to notify a reception module about data storage in the data storage region. A data acquisition section receives a request for data reception from the reception module to acquire data from the data storage region.

Abstract: The inter-module communication apparatus comprises: a first module and a second module which operate individually on a processor; a common memory interposed between the first module and the second module for functioning as a communication medium; a plurality of communication paths provided to the common memory for connecting the first module and the second module to be communicable; a transmission unit for transmitting communication data from the first module to the second module; and a reception unit for receiving the communication data transmitted from the first module by the second module.

Abstract: A semiconductor integrated circuit device includes: a first semiconductor chip including a CPU and a debug basic circuit section for verifying operation of a program executed by the CPU; and a second semiconductor chip retained over a principal surface of the first semiconductor chip and including a debug extension circuit section electrically connected to the CPU and the debug basic circuit section. The debug basic circuit section includes a debug command analyzing section for analyzing a command input from outside. The debug extension circuit section formed in the second semiconductor chip includes a debugging function circuit section including at least one debug circuit.

Abstract: A semiconductor integrated circuit device includes: a first semiconductor chip including a CPU and a debug basic circuit section for verifying operation of a program executed by the CPU; and a second semiconductor chip retained over a principal surface of the first semiconductor chip and including a debug extension circuit section electrically connected to the CPU and the debug basic circuit section. The debug basic circuit section includes a debug command analyzing section for analyzing a command input from outside. The debug extension circuit section formed in the second semiconductor chip includes a debugging function circuit section including at least one debug circuit.

Abstract: A debugging apparatus is disclosed which verifies a program to be embedded into a target machine by running the program in an environment which is one or the target machine, an emulator, and a simulator. Each environment includes operation state information of the program and inputs and outputs the operation state information in a form unique to the environment.

Abstract: A program development system in which the debugging apparatus is informed of all of the optimization processes which have been performed. A primitive storage unit stores record information for the optimization processes. The input unit receives an input of a variable and a value, or an input of a line where execution is to be halted. The primitive combining unit obtains record information showing the optimization processes. The code execution unit executes the execution code. The variable operation unit obtains the value of a variable based on relations between variables and resources. The output unit displays the obtained value of the variable. The line display unit displays the program or the generated execution code. The line information display unit displays, in line units, information relating to the optimization performed for each line, The operation-possible variable display unit displays, for each line, variables which can be set and referred to in the line.