Abstract: A two-dimensional monochrome bit face display has a luminance resolution that is equal to or higher than that of a CRT monitor. In one implementation, a two-dimensional monochrome bit face display has a bit face in which each pixel is constituted by m sub-pixels and neutral density filters mounted on the m sub-pixels of a respective pixel have light transmittances proportional to values ½n where n is an integer. In another implementation, mask filters are mounted on the m sub-pixels and have windows with light transmittances that are proportional to values ½n. Alternatively, areas of the m sub-pixels are set in the same proportion. The luminance of each sub-pixel is electronically controlled to improve the luminance resolution of the bit face display.

Abstract: A two-dimensional monochrome bit face display has a luminance resolution that is equal to or higher than that of a CRT monitor. In one implementation, a two-dimensional monochrome bit face display has a bit face in which each pixel is constituted by m sub-pixels and neutral density filters mounted on the m sub-pixels of a respective pixel have light transmittances proportional to values ½n where n is an integer. In another implementation, mask filters are mounted on the m sub-pixels and have windows with light transmittances that are proportional to values ½n. Alternatively, areas of the m sub-pixels are set in the same proportion. The luminance of each sub-pixel is electronically controlled to improve the luminance resolution of the bit face display.

Abstract: An on-screen display system using scan line memories. Complex on-screen display, comprising multiple layers of on-screen display, is achieved using a pixel memory having a maximum capacity of two horizontal lines of display data. Compressed display data (e.g. character, icon, etc.) is read from RAM and expanded into pixel registers. Pixel data from the pixel registers is forwarded to pixel memory for on-screen display. The pixel memory is also written back into one of the pixel registers and the pixel registers are overlaid to form complex on-screen display data.

Abstract: The invention defines a new computer architecture that will simultaneously improve the efficiency of the instruction word, and the speed of program execution. Instruction word efficiency is important to maximizing the use of available program memory space. The architecture described features an instruction memory that is wider than the minimum instruction width and equal to the maximum instruction width. The architecture is comprised of three sections; instruction memory, instruction read shift register, and control logic. The instruction memory width is equal to the maximum instruction width M (bits); where M is a twos multiple of the minimum instruction width K (bits). Instructions of various sizes are loaded into program memory in discrete blocks of size K. Consequently some multi-byte (assuming K=8) instructions are broken up and therefore occupy a portion of two adjacent memory locations.

Abstract: In an image processing system with an on-screen display function, a method of storing data of a row buffer in the on-screen display is to provide to minimize the capacity of the buffer by storing both character data and color data into a signal row buffer, thereby displaying a great deal of information on a monitor. Also, a row buffer control circuit for simultaneously storing characters and color data in the row buffer comprises a control data storing circuit, a column controlling part, a row controlling part, and a signal processing part.

Abstract: A method and apparatus for displaying a bar image in two colors on a screen of a cathode ray tube are disclosed. The device includes a first memory for storing the information to be displayed, including the first color, and a second memory for storing the screen addresses where the images are to be displayed in a second color. It also includes a microprocessor for selecting information from the first memory to be displayed at specific addresses on the screen. When the address for display is the same as one stored in the second memory, the microprocessor causes information to be displayed in the second color instead of the first color.

Abstract: A fine adjustment tuning apparatus for televisions includes a key matrix part, a microcomputer part, a local osicillating part, and a red/green/blue mixer part. The method of storing the tuning data includes an initial mode setting step, an on screen display displaying step, a storing deciding step, an input time detecting step, and a key input routine implementing step. The present invention eliminates the need to fine tune each time a new channel is selected.

Abstract: The device of this invention controls a cathode ray tube (CRT) in order to display desired images on a selected region of the screen. Locations on the screen are identified by horizontal and vertical addresses. The device comprises means for storing information to be displayed on the screen of the cathode ray tube and a control means. The control means selects information for display and generates a display control signal for controlling the cathode ray tube. The display control signal causes the cathode ray tube to display the selected information and also indicates a predetermined vertical or horizontal address. When the display control signal indicates a horizontal address, the control means displays selected information only in the region of the screen above or below the horizontal address and not in the remainder of the screen.

Abstract: A tuning mode command identifying the channel transmission format being used in an addressable CATV system is transmitted via a plurality of encoded CATV channels for downloading in subscriber home terminals. Downloading at the home terminals is effected by executing a plurality of sequential tuning cycles each comprising sequentially tuning successive CATV channels configured according to a different transmission format until a channel is tuned on which encoded data is being accurately received.