Abstract: A debugger includes: a plurality of processor cores; and a scheduler configured to control an allocation of a plurality of basic modules to the processor cores based on an execution rule for enabling parallel execution of a program that is divided into the basic modules that are executable asynchronously with one another, the program being defined with the execution rule of the basic modules for executing the basic modules in time series, wherein the scheduler includes a break point setting module configured to set a group of break points that are designated through a graphical user interface.

Abstract: According to one embodiment, an image output method comprises causing a second signal processing unit to select a second channel and decode an image signal on the second channel while causing a first signal processing unit to continue outputting a decoded image on a first channel on the basis of an instruction to switch to the decoded image output on the second channel while the first signal processing unit is outputting the decoded image on the first channel, and switching from the decoded image output on the first channel from the first signal processing unit to the decoded image output on the second channel from the second signal processing unit as a result of the completion of the preparation of the decoded image signal output on the second channel by the second signal processing unit.