Patents by Inventor Motoi Ichihashi
Motoi Ichihashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230132912Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.Type: ApplicationFiled: November 1, 2021Publication date: May 4, 2023Inventors: James P. Mazza, Elizabeth Strehlow, Motoi Ichihashi, Xuelian Zhu, Jia Zeng
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Patent number: 11101170Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.Type: GrantFiled: July 12, 2019Date of Patent: August 24, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Motoi Ichihashi, Atsushi Ogino
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Publication number: 20190333801Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.Type: ApplicationFiled: July 12, 2019Publication date: October 31, 2019Inventors: Motoi ICHIHASHI, Atsushi OGINO
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Patent number: 10395980Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.Type: GrantFiled: February 21, 2018Date of Patent: August 27, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Motoi Ichihashi, Atsushi Ogino
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Publication number: 20190259649Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.Type: ApplicationFiled: February 21, 2018Publication date: August 22, 2019Inventors: Motoi ICHIHASHI, Atsushi OGINO
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Patent number: 9953699Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a static random access memory assist circuit and methods of implementation and manufacture. The structure includes at least one static random access memory (SRAM) cell and a read assist circuit structured to apply a negative voltage to the at least one SRAM cell upon asserting of a wordline of the at least one SRAM cell.Type: GrantFiled: July 7, 2016Date of Patent: April 24, 2018Assignee: GLOBALFOUNDRIES INC.Inventor: Motoi Ichihashi
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Publication number: 20180012648Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a static random access memory assist circuit and methods of implementation and manufacture. The structure includes at least one static random access memory (SRAM) cell and a read assist circuit structured to apply a negative voltage to the at least one SRAM cell upon asserting of a wordline of the at least one SRAM cell.Type: ApplicationFiled: July 7, 2016Publication date: January 11, 2018Inventor: Motoi ICHIHASHI
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Publication number: 20170373071Abstract: A semiconductor memory structure includes adjacent cross-sectionally rectangular-shaped bottom source and drain electrodes, the electrodes including n-type electrode(s) and p-type electrode(s), and vertical channel transistors on one or more of the n-type electrode(s) and one or more of the p-type electrode(s); each vertical channel transistor including a vertical channel and a gate electrode wrapped therearound, some of the transistors including pull-up transistors. The semiconductor memory structure further includes a routing gate electrode for each gate electrode, and a shared contact having at least two parts, each part situated over the routing gate electrodes for the pull-up transistors. A unit semiconductor memory cell, the semiconductor memory structure and a corresponding method of forming the memory structure are also provided.Type: ApplicationFiled: June 27, 2016Publication date: December 28, 2017Applicant: GLOBALFOUNDRIES Inc.Inventors: Kwan-Yong LIM, Motoi ICHIHASHI, Youngtag WOO, Deepak NAYAK
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Patent number: 9711511Abstract: A semiconductor memory structure (e.g., SRAM) includes vertical channels with a circular, square or rectangular cross-sectional shape. Each unit cell can include a single pull-up vertical transistor and either: one pull-down vertical transistor and one pass-gate vertical transistor; or two or more of each of the pull-down and pass-gate vertical transistors. The structure may be realized by providing adjacent layers of undoped semiconductor material, forming vertical channels for vertical transistors, the vertical channels situated on each of the adjacent layers, doping a first half of each of the adjacent layers with a n-type or p-type dopant, doping a second half of each of the adjacent layers with an opposite type dopant to that of the first half, forming wrap-around gates surrounding the vertical channels, and forming top electrodes for the vertical transistors.Type: GrantFiled: June 27, 2016Date of Patent: July 18, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Kwan-Yong Lim, Ryan Ryoung-Han Kim, Motoi Ichihashi, Youngtag Woo, Deepak Nayak
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Publication number: 20150295678Abstract: A 4B5B encoder converts an inputted 4-bit data into a pattern of a 5-bit data in which (i) the number of bits of consecutive “0” data values is permitted to be maximum two, and, simultaneously, (ii) maximum one bit of head end two bits is permitted to have a “0” data value and maximum one bit of tail end two bits is permitted to have a “0” data value. A 5N-bit command encoder converts a command into a command pattern in which the number of bits contained in consecutive “0” data values is permitted to be maximum two. The data after the conversion and the command after the conversion are converted into NRZI codes by an NRZI encoder.Type: ApplicationFiled: June 25, 2015Publication date: October 15, 2015Inventors: Masayoshi TERABE, Hirofumi YAMAMOTO, Motoi ICHIHASHI, Naoki SUGIYAMA
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Publication number: 20120327942Abstract: A communication network system including a plurality of nodes disposed on a communication bus, and where each of the nodes is capable of transitioning between a normal operation mode and a low electricity consumption mode. The communication network system controls only a required node, in order to communicate with such required node, by transitioning the required node from the low power mode to the normal operation mode. To control the mode of the required nodes, a controlling node keeps a signal change state of the communication bus for a period that is longer than a normal communication frame length. The required node determines whether the period of the signal change state is longer than a threshold of the required node itself, to output a wakeup signal to a control circuit.Type: ApplicationFiled: June 26, 2012Publication date: December 27, 2012Applicant: DENSO CORPORATIONInventors: Masayoshi Terabe, Motoi Ichihashi, Yuuki Horii, Takashi Abe
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Publication number: 20120324320Abstract: A 4B5B encoder converts an inputted 4-bit data into a pattern of a 5-bit data in which (i) the number of bits of consecutive “0” data values is permitted to be maximum two, and, simultaneously, (ii) maximum one bit of head end two bits is permitted to have a “0” data value and maximum one bit of tail end two bits is permitted to have a “0” data value. A 5N-bit command encoder converts a command into a command pattern in which the number of bits contained in consecutive “0” data values is permitted to be maximum two. The data after the conversion and the command after the conversion are converted into NRZI codes by an NRZI encoder.Type: ApplicationFiled: June 12, 2012Publication date: December 20, 2012Applicant: DENSO CORPORATIONInventors: Masayoshi Terabe, Hirofumi Yamamoto, Motoi Ichihashi, Naoki Sugiyama
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Patent number: 6859917Abstract: Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a chip. A first logic gate using a first pair of potentials VDDL, VSSL having a relatively small potential difference as an operation power source and a second logic gate using a second pair of potentials VDDH, VSSH having a relatively large potential difference as an operation power source commonly use substrate potentials VBP, VBN of MIS transistors. The second logic gate has a relatively high driving capability, and the first logic gate can operate on relatively low power. The MIS transistor has a threshold voltage which increases by a reverse substrate bias and decreases by a forward substrate bias. By commonly using the substrate potential, even in the case where different substrate bias states are generated at both of the logic gates, MOS transistors of the logic gates can be formed in the common well region.Type: GrantFiled: August 15, 2003Date of Patent: February 22, 2005Assignee: Renesas Technology Corp.Inventors: Yasuhisa Shimazaki, Motoi Ichihashi
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Patent number: 6842045Abstract: Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a chip. A first logic gate using a first pair of potentials VDDL, VSSL having a relatively small potential difference as an operation power source and a second logic gate using a second pair of potentials VDDH, VSSH having a relatively large potential difference as an operation power source commonly use substrate potentials VBP, VBN of MIS transistors. The second logic gate has a relatively high driving capability, and the first logic gate can operate on relatively low power. The MIS transistor has a threshold voltage which increases by a reverse substrate bias and decreases by a forward substrate bias. By commonly using the substrate potential, even in the case where different substrate bias states are generated at both of the logic gates, MOS transistors of the logic gates can be formed in the common well region.Type: GrantFiled: April 24, 2002Date of Patent: January 11, 2005Assignee: Renesas Technology Corp.Inventors: Yasuhisa Shimazaki, Motoi Ichihashi
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Patent number: 6831483Abstract: Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a chip. A first logic gate using a first pair of potentials VDDL, VSSL having a relatively small potential difference as an operation power source and a second logic gate using a second pair of potentials VDDH, VSSH having a relatively large potential difference as an operation power source commonly use substrate potentials VBP, VBN of MIS transistors. The second logic gate has a relatively high driving capability, and the first logic gate can operate on relatively low power. The MIS transistor has a threshold voltage which increases by a reverse substrate bias and decreases by a forward substrate bias. By commonly using the substrate potential, even in the case where different substrate bias states are generated at both of the logic gates, MOS transistors of the logic gates can be formed in the common well region.Type: GrantFiled: May 16, 2001Date of Patent: December 14, 2004Assignee: Renesas Technology Corp.Inventors: Yasuhisa Shimazaki, Motoi Ichihashi
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Publication number: 20040051556Abstract: Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a chip. A first logic gate using a first pair of potentials VDDL, VSSL having a relatively small potential difference as an operation power source and a second logic gate using a second pair of potentials VDDH, VSSH having a relatively large potential difference as an operation power source commonly use substrate potentials VBP, VBN of MIS transistors. The second logic gate has a relatively high driving capability, and the first logic gate can operate on relatively low power. The MIS transistor has a threshold voltage which increases by a reverse substrate bias and decreases by a forward substrate bias. By commonly using the substrate potential, even in the case where different substrate bias states are generated at both of the logic gates, MOS transistors of the logic gates can be formed in the common well region.Type: ApplicationFiled: August 15, 2003Publication date: March 18, 2004Applicant: Hitachi, Ltd.Inventors: Yasuhisa Shimazaki, Motoi Ichihashi
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Publication number: 20020113616Abstract: Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a chip. A first logic gate using a first pair of potentials VDDL, VSSL having a relatively small potential difference as an operation power source and a second logic gate using a second pair of potentials VDDH, VSSH having a relatively large potential difference as an operation power source commonly use substrate potentials VBP, VBN of MIS transistors. The second logic gate has a relatively high driving capability, and the first logic gate can operate on relatively low power. The MIS transistor has a threshold voltage which increases by a reverse substrate bias and decreases by a forward substrate bias. By commonly using the substrate potential, even in the case where different substrate bias states are generated at both of the logic gates, MOS transistors of the logic gates can be formed in the common well region.Type: ApplicationFiled: April 24, 2002Publication date: August 22, 2002Applicant: Hitachi, Ltd.Inventors: Yasuhisa Shimazaki, Motoi Ichihashi
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Publication number: 20010043085Abstract: Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a chip. A first logic gate using a first pair of potentials VDDL, VSSL having a relatively small potential difference as an operation power source and a second logic gate using a second pair of potentials VDDH, VSSH having a relatively large potential difference as an operation power source commonly use substrate potentials VBP, VBN of MIS transistors. The second logic gate has a relatively high driving capability, and the first logic gate can operate on relatively low power. The MIS transistor has a threshold voltage which increases by a reverse substrate bias and decreases by a forward substrate bias. By commonly using the substrate potential, even in the case where different substrate bias states are generated at both of the logic gates, MOS transistors of the logic gates can be formed in the common well region.Type: ApplicationFiled: May 16, 2001Publication date: November 22, 2001Inventors: Yasuhisa Shimazaki, Motoi Ichihashi