Abstract: A method of processing a substrate includes patterning a mask over a dielectric layer and etching openings in the dielectric layer. The dielectric layer is disposed over the substrate. The etching includes flowing an etchant, a polar or H-containing gas, and a phosphorus-halide gas. The method may further include forming contacts by filling the openings with a conductive material.

Abstract: A substrate processing method includes providing a substrate with a silicon-containing film in a chamber, supplying a process gas containing an HF gas, a phosphorus halide gas, and at least one gas selected from the group consisting of a C4H2F6 gas, a C4H2F8 gas, a C3H2F4 gas, and a C3H2F6 gas into the chamber to generate plasma, and etching the silicon-containing film in the substrate.

Abstract: A substrate processing method includes placing a substrate with a dielectric film on a substrate support in a chamber, and etching the dielectric film with plasm generated from a reaction gas containing an HF gas and at least one CxHyFz gas selected from the group consisting of a C4H2F6 gas, a C4H2F8 gas, a C3H2F4 gas, and a C3H2F6 gas. The etching includes setting the substrate support at a temperature of 0° C. or lower and setting the HF gas to a flow rate greater than a flow rate of the CxHyFz gas.

Abstract: A semiconductor memory includes a plurality of nonvolatile memory cells arranged in a matrix and coupled to control gate lines, selection gate lines, bit lines, and source lines, and includes a source line control unit. The source line control unit, at a time of program operation, sets one of the source lines coupled to a row of the memory cells including a program memory cell to a high level voltage, and sets at least one of the remaining source lines coupled to a row of a non-program memory cells to be higher than a low level voltage of the selection gate lines and to be lower than the high level voltage of an unselection bit line. Thereby, a leak current lowering a voltage of the source lines at the time of program operation can be blocked off, and a program operation time may be shortened.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A semiconductor memory includes a memory cell having a cell transistor and a selection transistor, a control gate line coupled to a gate electrode of the cell transistor, a selection gate line coupled to a gate electrode of the selection transistor, a selection gate driver configured to apply a voltage to the selection gate line, a switch circuit configured to couple the control gate line to the selection gate line, and a level converting unit coupled to the control gate line and a voltage line and configured to convert a voltage of the control gate line into a voltage of the voltage line.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A semiconductor memory includes a plurality of nonvolatile memory cells arranged in a matrix and coupled to control gate lines, selection gate lines, bit lines, and source lines, and includes a source line control unit. The source line control unit, at a time of program operation, sets one of the source lines coupled to a row of the memory cells including a program memory cell to a high level voltage, and sets at least one of the remaining source lines coupled to a row of a non-program memory cells to be higher than a low level voltage of the selection gate lines and to be lower than the high level voltage of an unselection bit line. Thereby, a leak current lowering a voltage of the source lines at the time of program operation can be blocked off, and a program operation time may be shortened.

Abstract: A nonvolatile semiconductor memory that improved a read rate. In a memory cell array in which each memory cell includes two storage areas, thresholds of outer storage areas of two memory cells which are symmetrical with respect to two adjacent bit lines are set so as to create a pair relation between them. A word line selection circuit applies read voltage to a word line to which the two memory cells to be read are connected. A bit line selection circuit applies ground voltage to two bit lines just outside the two memory cells and applies predetermined read voltage to two bit lines inside the two memory cells. A read conversion circuit compares drain currents which run through the two memory cells activated by the word line selection circuit and the bit line selection circuit, and converts the drain currents into data.

Abstract: A semiconductor memory includes a memory cell having a cell transistor and a selection transistor, a control gate line coupled to a gate electrode of the cell transistor, a selection gate line coupled to a gate electrode of the selection transistor, a selection gate driver configured to apply a voltage to the selection gate line, a switch circuit configured to couple the control gate line to the selection gate line, and a level converting unit coupled to the control gate line and a voltage line and configured to convert a voltage of the control gate line into a voltage of the voltage line.

Abstract: The conventional Pt/second component/electroconductive carbon type anode materials to be utilized as polymer fuel cell-oriented solid electrolytes and in various sensors have been problematic in several aspects such as activities for oxidizing CO, price, and the like. The present invention aims at providing a Pt/CeO2/electroconductive carbon nano-hetero anode material that is free of such problems, and a production method thereof.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: The conventional Pt/second component/electroconductive carbon type anode materials to be utilized as polymer fuel cell-oriented solid electrolytes and in various sensors have been problematic in several aspects such as activities for oxidizing CO, price, and the like. The present invention aims at providing a Pt/CeO2/electroconductive carbon nano-hetero anode material that is free of such problems, and a production method thereof.

Abstract: A nonvolatile semiconductor memory that improved a read rate. In a memory cell array in which each memory cell includes two storage areas, thresholds of outer storage areas of two memory cells which are symmetrical with respect to two adjacent bit lines are set so as to create a pair relation between them. A word line selection circuit applies read voltage to a word line to which the two memory cells to be read are connected. A bit line selection circuit applies ground voltage to two bit lines just outside the two memory cells and applies predetermined read voltage to two bit lines inside the two memory cells. A read conversion circuit compares drain currents which run through the two memory cells activated by the word line selection circuit and the bit line selection circuit, and converts the drain currents into data.

Abstract: A function switching part has a pair of programming elements programmed to different logic values. A decision circuit in the function switching part outputs a logic level according to a difference between the currents flowing in the programming elements, while the power supply voltage rises at the power-on. The operating specification of an option functional part is switched according to the logic level output from the decision circuit. That is, the operating specification of the option functional part is automatically decided according to the program state of the programming element before the power-on operation is completed. The read operation for the programming element need not be performed for deciding the operating specification of the option functional part. Since the initial process after the power-on period is simplified, the period from when the power is turned on to when the normal operation begins can be shortened.

Abstract: A function switching part has a pair of programming elements programmed to different logic values. A decision circuit in the function switching part outputs a logic level according to a difference between the currents flowing in the programming elements, while the power supply voltage rises at the power-on. The operating specification of an option functional part is switched according to the logic level output from the decision circuit. That is, the operating specification of the option functional part is automatically decided according to the program state of the programming element before the power-on operation is completed. The read operation for the programming element need not be performed for deciding the operating specification of the option functional part. Since the initial process after the power-on period is simplified, the period from when the power is turned on to when the normal operation begins can be shortened.