Abstract: Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.

Abstract: A variable-length code decoding apparatus that decodes a bitstream includes: a storage unit that stores a variable-length code table; a bitstream cutout unit that outputs a bit string of a fixed length; a reference unit that outputs decoded data and a code length with reference to the storage unit; a determination unit that determines whether a bit string of the fixed length is accumulated; a determination unit that determines whether a bit string of a length that is shorter than the fixed length is accumulated; and a selection unit that selects one of the determination results from the determination units. The bitstream cutout unit sets a starting bit based on the selected determination result, and the selection unit switches the selection of the determination results from the determination units.

Abstract: Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.

Abstract: An information processing device, including: a processing unit; a peripheral circuit module; and a boot address register, wherein the information processing device comprises a first operation mode and a second operation mode having an operating current which is lower than that of said first operation mode, wherein the boot address register holds an address of an instruction to be executed by said processing unit first when the boot address register returns from said second operation mode to said first operation mode, wherein the address is output from said boot address to the processing unit when said information processing device shifts from said second operation mode to said first operation mode.

Abstract: An image memory access control unit (502) judges whether or not an additional pixel required for motion compensation is necessary, the additional pixel not being included in a plurality of pixels forming an image shown by a reference block. When the additional pixel is judged to be necessary, a yet-to-be-obtained-pixel interpolating unit (503) generates at least one additional pixel, and generates a reference image to be used for motion compensation using the generated at least one additional pixel and at least a part of the image shown by the reference block. When the additional pixel is judged to be unnecessary, the yet-to-be-obtained-pixel interpolating unit (503) outputs at least a part of the image shown by the reference block as the reference image.

Abstract: A variable-length code decoding apparatus that decodes a bitstream includes: a storage unit that stores a variable-length code table; a bitstream cutout unit that outputs a bit string of a fixed length; a reference unit that outputs decoded data and a code length with reference to the storage unit; a determination unit that determines whether a bit string of the fixed length is accumulated; a determination unit that determines whether a bit string of a length that is shorter than the fixed length is accumulated; and a selection unit that selects one of the determination results from the determination units. The bitstream cutout unit sets a starting bit based on the selected determination result, and the selection unit switches the selection of the determination results from the determination units.

Abstract: In an information processor including memory devices such as DRAMs and others, by reducing the power consumption of memory devices and efficiently repairing defect bits, a highly reliable information processor is realized. In an information processor including an external memory such as a DRAM, a second memory whose power consumption at the access time is smaller than that of the external memory is disposed, and cache data of the external memory and repair data are stored in this second memory. To an input address given from a central processing unit via a primary cache controller, a memory controller determines a hit or a miss with reference to a tag memory for cache and a tag memory for repair, and when one or both of tag memory for cache and a tag memory for repair are hit, it accesses the second memory.

Abstract: To reduce bandwidth in an image data decoding device including a decoding unit which obtains image data inputted into the image data decoding device and decodes the obtained image data. A decoding device (100) which decodes a bitstream of an image, includes: a code converting unit (101) which converts the bitstream inputted to the decoding device (100) into a bitstream coded using a second coding rule in which a maximum code length is shorter than in a first coding rule by which the bitstream has been coded; and an image decoder (103) which obtains the bitstream that has been converted by the code converting unit (101), and decodes the obtained bitstream.

Abstract: Abstract An information processing device, including: a processing unit; a peripheral circuit module; and a boot address register, wherein the information processing device comprises a first operation mode and a second operation mode having an operating current which is lower than that of said first operation mode, wherein the boot address register holds an address of an instruction to be executed by said processing unit first when the boot address register returns from said second operation mode to said first operation mode, wherein the address is output from said boot address to the processing unit when said information processing device shifts from said second operation mode to said first operation mode.

Abstract: A mechanism of making a low standby current caused by power off compatible with a fast return operation from a standby caused by an interrupt is realized. An information processing device has a first area that includes a central processing unit and peripheral circuit modules, a second area having information holding circuits for holding values of registers contained in the peripheral circuit modules, and a first power switch for controlling supply of a current to the first area. When the information processing device operates in a first mode, an operating current is supplied to the first area and the second area. When the information processing device operates in a second mode, the first power switch is controlled so that the supply of the current to the first area can be shut off, and the supply of the current to the second area is continued.

Abstract: A data processor having: an instruction fetch unit for acquiring an instruction; and an instruction execution unit for execution, by pipeline processing, the instruction acquired by the instruction fetch unit. In the data processor, the instruction execution unit includes an execution pipeline pipelined into two or more stages for execution of the execution instruction, and an execution pipeline control unit capable of changing a stage to arrange an operation by the execution unit in according to the number of wait cycles until data required for execution of the execution instruction is fixed. The stage, where an operation by the execution unit is arranged, is changed according to the number of wait cycles until the data is fixed, whereby the number of input-fixing wait cycles increased by pipelining cache access can be reduced.

Abstract: In an information processor including memory devices such as DRAMs and others, by reducing the power consumption of memory devices and efficiently repairing defect bits, a highly reliable information processor is realized. In an information processor including an external memory such as a DRAM, a second memory whose power consumption at the access time is smaller than that of the external memory is disposed, and cache data of the external memory and repair data are stored in this second memory. To an input address given from a central processing unit via a primary cache controller, a memory controller determines a hit or a miss with reference to a tag memory for cache and a tag memory for repair, and when one or both of tag memory for cache and a tag memory for repair are hit, it accesses the second memory.

Abstract: A data processor having: an instruction fetch unit for acquiring an instruction; and an instruction execution unit for execution, by pipeline processing, the instruction acquired by the instruction fetch unit. In the data processor, the instruction execution unit includes an execution pipeline pipelined into two or more stages for execution of the execution instruction, and an execution pipeline control unit capable of changing a stage to arrange an operation by the execution unit in according to the number of wait cycles until data required for execution of the execution instruction is fixed. The stage, where an operation by the execution unit is arranged, is changed according to the number of wait cycles until the data is fixed, whereby the number of input-fixing wait cycles increased by pipelining cache access can be reduced.

Abstract: A mechanism of making a low standby current caused by power off compatible with a fast return operation from a standby caused by an interrupt is realized. An information processing device has a first area that includes a central processing unit and peripheral circuit modules, a second area having information holding circuits for holding values of registers contained in the peripheral circuit modules, and a first power switch for controlling supply of a current to the first area. When the information processing device operates in a first mode, an operating current is supplied to the first area and the second area. When the information processing device operates in a second mode, the first power switch is controlled so that the supply of the current to the first area can be shut off, and the supply of the current to the second area is continued.