Abstract: A switching regulator, has first and second switching regulator units, and first and second PLL circuit units that are provided in the first and second switching regulator units respectively, input first and second control pulse signals (PIN1, PIN2) respectively, phases of which are shifted from each other, and control the first timing (T1) of performing non-conduction control on the first switching element (LMOS). The first and second control pulse signals each is controlled to have a frequency corresponding to a voltage-boosted level of the output terminal to maintain the output voltage at predetermined voltage.

Abstract: A power supply device has a first node to which an input voltage is input, a second node, a third node from which an output voltage is output, a first switching circuit electrically connecting the first node and the second node and a resonance circuit electrically connecting the second node and the third node. The power supply device converts the input voltage into the output voltage through an intermediate voltage of the second node. A first timing circuit is operable to turn on and turn off the first switching circuit. When the intermediate voltage becomes equal to or larger than a first predetermined voltage, the first timing circuit turns on the first switching circuit after a first predetermined time period.

Abstract: A switching regulator for inputting a power source, supplying output power to an external circuit, and adjusting the output voltage to a target voltage, the switching regulator has a switching regulator circuit having first and second transistors, a feedback circuit that receives the output voltage, and outputs a control pulse signal at a frequency in accordance with the received output voltage; a PLL circuit unit having a PLL circuit, and a first control signal generating circuit that outputs the first control signal for controlling the first transistor; and a drive circuit that outputs a second control signal that controls the second transistor; and a control circuit that monitors the period of the PLL output pulse and the control pulse signal, and controls the ON and OFF timing of the second transistor when a difference of monitored periods.

Abstract: The switching regulator has a first switching regulator circuit for outputting a variable power according to a pulse width modulation pulse to be supplied; a second switching regulator circuit for outputting or stopping a constant power according to a control signal to be supplied; and a control circuit for controlling the first switching regulator circuit and the second switching regulator circuits. The control circuit increases the variable power of the first switching regulator circuit by an amount greater than a regular amount if a detected voltage changes from a status higher than the target voltage to a status lower than the target voltage, and decreases the variable power of the first switching regulator circuit by an amount greater than the regular amount if the detected voltage changes from a status lower than the target voltage to a status higher than the target voltage.

Abstract: A half bridge step-up switching regulator is configured including an output voltage adjusting switch element Q1 for adjusting an output voltage; a synchronous switch element Q2, connected in series with the output voltage adjusting switch element Q1, that is complementary ON operated when the output voltage adjusting switch element Q1 is turned OFF; a voltage detecting section 10 for detecting the voltage at a connecting node of the switch elements in time of turn-OFF of the synchronous switch element; and a soft switch control section 20 for adjusting the timing of turn-OFF of the synchronous switch element Q2 based on the voltage fluctuation detected by the voltage detecting section 10 to perform zero current switching control.

Abstract: A switching regulator, has first and second switching regulator units, and first and second PLL circuit units that are provided in the first and second switching regulator units respectively, input first and second control pulse signals (PIN1, PIN2) respectively, phases of which are shifted from each other, and control the first timing (T1) of performing non-conduction control on the first switching element (LMOS). The first and second control pulse signals each is controlled to have a frequency corresponding to a voltage-boosted level of the output terminal to maintain the output voltage at predetermined voltage.

Abstract: A control apparatus to which plural power devices are connected via a communication line. The power devices send data indicating a self-diagnostic result to the control apparatus by serial communications via the communication line. A CPU ignores serial communication data when a low-voltage detection circuit detects an abnormal drop in power source voltage. A period for ignoring data is set to time at which a completion of serial communication with all the power devices is determined by counting the number of communications by a counter. Even in case where an influence by the drop in power source voltage remains after recovery of the power source voltage due to communication delay, data that may includes abnormality is ignored and only self-diagnostic data with high reliability is used.

Abstract: A control apparatus to which plural power devices are connected via a communication line. The power devices send data indicating a self-diagnostic result to the control apparatus by serial communications via the communication line. A CPU ignores serial communication data when a low-voltage detection circuit detects an abnormal drop in power source voltage. A period for ignoring data is set to time at which a completion of serial communication with all the power devices is determined by counting the number of communications by a counter. Even in case where an influence by the drop in power source voltage remains after recovery of the power source voltage due to communication delay, data that may includes abnormality is ignored and only self-diagnostic data with high reliability is used.