Abstract: A memory driver includes a word line driver circuit, a reference circuit, and a bias circuit. The word line driver circuit is coupled to a word line and configured to selectively provide a reference voltage from a reference node to the word line according to an input signal. The reference circuit has a capacitor coupled to the reference node. The reference circuit is configured to store the reference voltage on the capacitor and lower the reference voltage from a first voltage level to a second voltage level when the reference voltage is provided by the word line driver circuit from the reference node to the word line. The bias circuit coupled to the reference node and configured to regulate the reference voltage at the reference node by the second voltage level.

Abstract: A circuit includes a first capacitive device coupled between first and second nodes, a second capacitive device coupled between third and fourth nodes, a first switching device coupled between the first node and a voltage node, a second switching device coupled between the second node and a reference voltage node, a third switching device coupled between the third node and the voltage node, a fourth switching device coupled between the fourth node and the reference voltage node, fifth through eighth switching devices coupled between the respective first through fourth nodes and an output node, and first and second variable capacitance devices including first terminals coupled to either the respective first and third nodes or the respective second and fourth nodes.

Abstract: A memory driver includes a word line driver circuit, a reference circuit, and a bias circuit. The word line driver circuit is coupled to a word line and configured to selectively provide a reference voltage from a reference node to the word line according to an input signal. The reference circuit has a capacitor coupled to the reference node. The reference circuit is configured to store the reference voltage on the capacitor and lower the reference voltage from a first voltage level to a second voltage level when the reference voltage is provided by the word line driver circuit from the reference node to the word line. The bias circuit coupled to the reference node and configured to regulate the reference voltage at the reference node by the second voltage level.

Abstract: A semiconductor device and a method of operating the semiconductor device are disclosed. In one aspect, the semiconductor device includes a memory cell connected to a bit line, and a biasing circuit configured to output a first bias voltage and a second bias voltage, the first bias voltage generated based on a threshold voltage of a p-type transistor, and the second bias voltage generated based on a threshold voltage of an n-type transistor. The semiconductor device includes a step-down circuit connected to the bit line and configured to receive the first and second bias voltages, the step-down circuit configured to output an output voltage to charge the bit line based on the first and second bias voltages.

Abstract: A semiconductor device includes a first well and a second well. The first well is configured to operate as a back gate terminal of a first transistor. The second well is separated from the first well, and is configured to operate as a back gate terminal of a second transistor. Each of a first source/drain terminal of the second transistor, and a first source/drain terminal of the first transistor and the back gate terminal of the first transistor are coupled to each other.

Abstract: A memory driver includes a word line driver circuit, a reference circuit, and a bias circuit. The word line driver circuit is coupled to a word line and configured to selectively provide a reference voltage from a reference node to the word line according to an input signal. The reference circuit has a capacitor coupled to the reference node. The reference circuit is configured to store the reference voltage on the capacitor and lower the reference voltage from a first voltage level to a second voltage level when the reference voltage is provided by the word line driver circuit from the reference node to the word line. The bias circuit coupled to the reference node and configured to regulate the reference voltage at the reference node by the second voltage level.

Abstract: A semiconductor storage device according to the present embodiment includes an antifuse element and a first element. The antifuse element is connected at one end to a first terminal to which a write voltage is applicable, and includes a gate oxide film. The first element is connected to the other end of the antifuse element. In a case where the write voltage that breaks the gate oxide film is supplied to the first terminal and the gate oxide film is not broken, the first element supplies a second potential that makes a potential difference between the one end and the other end less than a potential that breaks the gate oxide film, to the other end.

Abstract: A semiconductor storage device according to the present embodiment includes an antifuse element and a first element. The antifuse element is connected at one end to a first terminal to which a write voltage is applicable, and includes a gate oxide film. The first element is connected to the other end of the antifuse element. In a case where the write voltage that breaks the gate oxide film is supplied to the first terminal and the gate oxide film is not broken, the first element supplies a second potential that makes a potential difference between the one end and the other end less than a potential that breaks the gate oxide film, to the other end.

Abstract: A step-down circuit includes a first transistor of N-type having a channel between an input terminal and a first node, and a gate to which a reference voltage that is lower than a peak value of an AC voltage applied to the input terminal is applied, a second transistor of P-type having a channel between the input terminal and a second node, and a gate to which the reference voltage is applied, a third transistor of N-type having a channel between the first node and an output terminal, and a gate to which the AC voltage is applied, a fourth transistor of P-type having a channel between the second node and the output terminal, and a gate to which the AC voltage is applied, a first capacitor connected between the first node and the second node, and a second capacitor connected between the output terminal and a reference potential terminal.