Patents by Inventor Motoki Tokumasu

Motoki Tokumasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory and holding device
    Patent number: 6617902
    Abstract: A semiconductor holding device comprises a first transistor circuit including a P type first transistor connected to a first power source, an N type second transistor connected to the first transistor and an N type third transistor connected to the second transistor and a second power source, and a second transistor circuit including a P type fourth transistor connected to the first power source, an N type fifth transistor connected to the fourth transistor and an N type sixth transistor connected between the fifth transistor and the second power source, an input signal being supplied to gates of the P type first transistor and the N type second transistor, a clock signal being supplied to gates of the N type third and sixth transistors, a node of the first and second transistors being connected to gates of the fourth and fifth transistors, and a node of the fourth and fifth transistors serving as an output node.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: September 9, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Motoki Tokumasu, Hiroshige Fujii
  • Semiconductor memory and holding device
    Publication number: 20020149409
    Abstract: A semiconductor holding device comprises a first transistor circuit including a P type first transistor connected to a first power source, an N type second transistor connected to the first transistor and an N type third transistor connected to the second transistor and a second power source, and a second transistor circuit including a P type fourth transistor connected to the first power source, an N type fifth transistor connected to the fourth transistor and an N type sixth transistor connected between the fifth transistor and the second power source, an input signal being supplied to gates of the P type first transistor and the N type second transistor, a clock signal being supplied to gates of the N type third and sixth transistors, a node of the first and second transistors being connected to gates of the fourth and fifth transistors, and a node of the fourth and fifth transistors serving as an output node.
    Type: Application
    Filed: March 21, 2002
    Publication date: October 17, 2002
    Inventors: Motoki Tokumasu, Hiroshige Fujii