Patents by Inventor Motoki Wakano

Motoki Wakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10384314
    Abstract: A metal particle having a particle diameter of 10 ?m or more and 1000 ?m or less and includes Cu and trace elements and a total mass content of P and S, among other trace elements, is 3 ppm or more and 30 ppm or less. A method for producing a metal particle including producing a molten metal material by melting a metal material in a crucible, wherein Cu as determined in GDMS analysis is over 99.995% and a total of P and S is 3 ppm or more and 30 ppm or less; applying a pressure of 0.05 MPa or more and 1.0 MPa or less to drip the molten metal material through an orifice, thereby producing a molten metal droplet; and rapidly solidifying the molten metal droplet using an inert gas whose oxygen concentration is 1000 ppm or less.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: August 20, 2019
    Assignee: HITACHI METALS, LTD.
    Inventor: Motoki Wakano
  • Publication number: 20180056451
    Abstract: A metal particle having a particle diameter of 10 ?m or more and 1000 ?m or less and includes Cu and trace elements and a total mass content of P and S, among other trace elements, is 3 ppm or more and 30 ppm or less. A method for producing a metal particle including producing a molten metal material by melting a metal material in a crucible, wherein Cu as determined in GDMS analysis is over 99.995% and a total of P and S is 3 ppm or more and 30 ppm or less; applying a pressure of 0.05 MPa or more and 1.0 MPa or less to drip the molten metal material through an orifice, thereby producing a molten metal droplet; and rapidly solidifying the molten metal droplet using an inert gas whose oxygen concentration is 1000 ppm or less.
    Type: Application
    Filed: March 23, 2016
    Publication date: March 1, 2018
    Inventor: Motoki WAKANO
  • Patent number: 8368195
    Abstract: A semiconductor device having stacked semiconductor chips is provided wherein alignment of even thin semiconductor chips of a large warpage is easy and thus high assembling accuracy and high reliability are ensured. Semiconductor chips having hollow through-silicon via electrodes each formed with a tapered portion are melt-joined using solder balls each having a core of a material higher in melting point than solder. When melt-joining the semiconductor chips, the temperature is raised while imparting an urging load to stacked semiconductor chips, thereby correcting warpage of the semiconductor chips. In each chip-to-chip connection thus formed, if the connection is to prevent the occurrence of stress around the electrode due to the urging load, a solder ball having a core of a smaller diameter than in the other connections is used in the connection.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: February 5, 2013
    Assignee: Hitachi Metals, Ltd.
    Inventors: Hisashi Tanie, Takeyuki Itabashi, Nobuhiko Chiwata, Motoki Wakano
  • Patent number: 8053908
    Abstract: A novel structure capable of reducing the stress in the insulating layer in the semiconductor element and thereby securing reliability is provided. When the semiconductor element and the substrate are connected with a solder, the stress generated in the insulating layer is reduced by placing a spherical core made of a material having a greater rigidity inside the solder and satisfying the following inequalities: 1 GPa<(Young's modulus of a encapsulation resin)<30 GPa, 20 ppm/k<(linear coefficient of expansion of the encapsulation resin)<200 ppm/k, and 10 MPa<(yield stress of the solder at room temperature)<30 MPa. At the time of connection, the thickness of the solder to be placed between the land on the surface of the semiconductor element and the core is adjusted to 1/10 or less of the terminal pitch.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: November 8, 2011
    Assignee: Hitachi Metals, Ltd.
    Inventors: Hisashi Tanie, Nobuhiko Chiwata, Motoki Wakano, Takeyuki Itabashi
  • Patent number: 7901782
    Abstract: The invention provides a solder alloy containing, by mass, 2.0 to 15.0% of Ag, 0.1 to 6.0% of Al, 0.01 to 0.50% of Y, the balance being Sn and unavoidable impurities. The solder alloy preferably contains 0.01 to 0.50% of Ge by mass. The solder alloy of the invention is suited to bonding oxides together and the oxides preferably comprise glass. The invention provides a glass bonded body formed by bonding glasses with the use of the solder alloy.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: March 8, 2011
    Assignee: Hitachi Metals, Ltd.
    Inventors: Nobuhiko Chiwata, Minoru Yamada, Motoki Wakano
  • Publication number: 20100193936
    Abstract: A novel structure capable of reducing the stress in the insulating layer in the semiconductor element and thereby securing reliability is provided. When the semiconductor element and the substrate are connected with a solder, the stress generated in the insulating layer is reduced by placing a spherical core made of a material having a greater rigidity inside the solder and satisfying the following inequalities: 1 GPa<(Young's modulus of a encapsulation resin)<30 GPa, 20 ppm/k<(linear coefficient of expansion of the encapsulation resin)<200 ppm/k, and 10 MPa<(yield stress of the solder at room temperature)<30 MPa. At the time of connection, the thickness of the solder to be placed between the land on the surface of the semiconductor element and the core is adjusted to 1/10 or less of the terminal pitch.
    Type: Application
    Filed: January 27, 2010
    Publication date: August 5, 2010
    Inventors: Hisashi TANIE, Nobuhiko Chiwata, Motoki Wakano, Takeyuki Itabashi
  • Publication number: 20100171209
    Abstract: A semiconductor device having stacked semiconductor chips is provided wherein alignment of even thin semiconductor chips of a large warpage is easy and thus high assembling accuracy and high reliability are ensured. Semiconductor chips having hollow through-silicon via electrodes each formed with a tapered portion are melt-joined using solder balls each having a core of a material higher in melting point than solder. When melt-joining the semiconductor chips, the temperature is raised while imparting an urging load to stacked semiconductor chips, thereby correcting warpage of the semiconductor chips. In each chip-to-chip connection thus formed, if the connection is to prevent the occurrence of stress around the electrode due to the urging load, a solder ball having a core of a smaller diameter than in the other connections is used in the connection.
    Type: Application
    Filed: January 5, 2010
    Publication date: July 8, 2010
    Inventors: Hisashi Tanie, Takeyuki Itabashi, Nobuhiko Chiwata, Motoki Wakano
  • Publication number: 20080241552
    Abstract: The invention provides a solder alloy containing, by mass, 2.0 to 15.0% of Ag, 0.1 to 6.0% of Al, 0.01 to 0.50% of Y, the balance being Sn and unavoidable impurities. The solder alloy preferably contains 0.01 to 0.50% of Ge by mass. The solder alloy of the invention is suited to bonding oxides together and the oxides preferably comprise glass. The invention provides a glass bonded body formed by bonding glasses with the use of the solder alloy.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 2, 2008
    Applicant: Hitachi Metals, Ltd.
    Inventors: Nobuhiko CHIWATA, Minoru Yamada, Motoki Wakano