Patents by Inventor Motoki Yamazaki

Motoki Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12252775
    Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.
    Type: Grant
    Filed: April 12, 2024
    Date of Patent: March 18, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tetsunori Maruyama, Yuki Imoto, Hitomi Sato, Masahiro Watanabe, Mitsuo Mashiyama, Kenichi Okazaki, Motoki Nakashima, Takashi Shimazu
  • Patent number: 12218144
    Abstract: The stability of a step of processing a wiring formed using copper, aluminum, gold, silver, molybdenum, or the like is increased. Moreover, the concentration of impurities in a semiconductor film is reduced. Moreover, the electrical characteristics of a semiconductor device are improved. In a transistor including an oxide semiconductor film, an oxide film in contact with the oxide semiconductor film, and a pair of conductive films being in contact with the oxide film and including copper, aluminum, gold, silver, molybdenum, or the like, the oxide film has a plurality of crystal parts and has c-axis alignment in the crystal parts, and the c-axes are aligned in a direction parallel to a normal vector of a top surface of the oxide semiconductor film or the oxide film.
    Type: Grant
    Filed: December 7, 2023
    Date of Patent: February 4, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Yasutaka Nakazawa, Yukinori Shima, Masami Jintyou, Masayuki Sakakura, Motoki Nakashima
  • Patent number: 11346471
    Abstract: The present invention provides a corrugated tube and a method for manufacturing the same capable of improving workability in press-fitting work of a pipe or a quick connector. A corrugated tube includes a flexible section having a first corrugated section and a second corrugated section, and straight sections integrally formed at both ends of the flexible section respectively. A length of valley portions in an axial center direction is larger than a length of valley portions in the first corrugated section, thereby allows a pitch P2 of mountain portions in the second corrugated section provided between the straight section and the first corrugated section to be larger than a pitch P1 of mountain portions in the first corrugated section.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: May 31, 2022
    Assignee: NITTA CORPORATION
    Inventors: Yuto Nakahira, Motoki Yamazaki
  • Publication number: 20210041044
    Abstract: The present invention provides a corrugated tube and a method for manufacturing the same capable of improving workability in press-fitting work of a pipe or a quick connector. A corrugated tube includes a flexible section having a first corrugated section and a second corrugated section, and straight sections integrally formed at both ends of the flexible section respectively. A length of valley portions in an axial center direction is larger than a length of valley portions in the first corrugated section, thereby allows a pitch P2 of mountain portions in the second corrugated section provided between the straight section and the first corrugated section to be larger than a pitch P1 of mountain portions in the first corrugated section.
    Type: Application
    Filed: March 6, 2019
    Publication date: February 11, 2021
    Inventors: Yuto NAKAHIRA, Motoki YAMAZAKI
  • Patent number: 7741708
    Abstract: A semiconductor device having a plurality of semiconductor chips mounted on a lead frame (10) and required portions covered with seal portions in which: the plurality of semiconductor chips are divided into a first group of semiconductor chips (Dx to Dz) and a second group of semiconductor chips (Du to Dw and Thx to Thz); both groups of semiconductor chips are mounted on the lead frame (10) at a distance from each other; the seal portions are comprised of first and second resin-seal portions (41 and 42) which cover the first and second groups of semiconductor chips, respectively, along with required portions of the lead frame; both resin-seal portions are mechanically coupled with each other by coupling portions; and a group of read terminals respectively connected to circuits within the first resin-seal portion and circuits within the second resin-seal portion are led out through a gap between the first resin-seal portion (41) and the second resin-seal portion (42).
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: June 22, 2010
    Assignee: Kokusan Denki Co., Ltd.
    Inventors: Shuichi Muramatsu, Hidetoshi Suzuki, Tomoyuki Sato, Kazuo Hara, Motoki Yamazaki, Masaki Asari, Hirofumi Yamaguchi
  • Publication number: 20080290477
    Abstract: A semiconductor device having a plurality of semiconductor chips mounted on a lead frame (10) and required portions covered with seal portions in which: the plurality of semiconductor chips are divided into a first group of semiconductor chips (Dx to Dz) and a second group of semiconductor chips (Du to Dw and Thx to Thz); both groups of semiconductor chips are mounted on the lead frame (10) at a distance from each other; the seal portions are comprised of first and second resin-seal portions (41 and 42) which cover the first and second groups of semiconductor chips, respectively, along with required portions of the lead frame; both resin-seal portions are mechanically coupled with each other by coupling portions; and a group of read terminals respectively connected to circuits within the first resin-seal portion and circuits within the second resin-seal portion are led out through a gap between the first resin-seal portion (41) and the second resin-seal portion (42).
    Type: Application
    Filed: December 9, 2005
    Publication date: November 27, 2008
    Applicant: Kokusan Denki Co., Ltd.
    Inventors: Shuichi Muramatsu, Hidetoshi Suzuki, Tomoyuki Sato, Kazuo Hara, Motoki Yamazaki, Masaki Asari, Hirofumi Yamaguchi
  • Patent number: 5712038
    Abstract: A vibration damper material 1 composed of a laminated sheet having a base stock layer 3, a resilient layer 4, an primer layer 5, an organic component barrier layer 6 and an adhesive layer 7 successively laminated in that order from one to the other side thereof, and a release liner 8 stuck on the adhesive layer 7. The resilient layer 4 is constituted by a resilient material containing a vehicle consisting of a member or a mixture of two or more members selected from the group of asphalt, rubber, synthetic resins and cellulose derivatives, synthetic resin powder, and an elastic material having an elongation rate of 500% or higher. The organic component barrier layer functions to block permeation therethrough of organic components such as tar and oil components which would otherwise tend to migrate into the adhesive layer from the resilient layer.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: January 27, 1998
    Assignee: Lintec Corporation
    Inventors: Motoki Yamazaki, Toshio Sugizaki, Masao Kogure, Takanori Saitoh