Abstract: In a data processing system, a processor issues a transfer request through a data transfer controller to an extended buffer memory to elicit an accept signal. If the accept signal is not returned from the buffer memory within a specified period, a first dummy signal is generated instead, and the controller notifies this fact to the processor and waits for the return of an advance notice from the buffer memory. If the advance notice is not returned within a specified period, a second dummy signal is generated instead to allow the controller to proceed to transfer data read out of the buffer memory to a main memory. The controller then waits for the return of a status report signal from the buffer memory. If the status report signal is not received within a specified period, a third dummy signal is generated instead to allow the controller to proceed to examine a status signal from the buffer memory to determine whether the transferred data has been correctly read out of the buffer memory.

Abstract: In an information processing system comprising a main memory device, a plurality of processors, a system controller between the main memory device and the processors, and an extended buffer memory for carrying out a data transfer operation to and from the main memory device, the system controller comprises a communication lock circuit for selectively indicating a locked state and an unlocked state representative of a state of the extended buffer memory. The communication lock circuit is accessed to detect the state of the extended buffer memory each time when either a lock instruction or a lock release instruction is issued from each processor before a data transfer request is delivered from each processor to the extended buffer memory.

Abstract: In a multiprocessor system, a request from a processor for data transfer between an external mass storage unit and a main memory is granted and a report indicating an event is supplied from the external storage unit if there is one to report. An event decoder decodes the reported event and makes a first decision if it is a sync-related event resulting from the execution of an instruction and makes a second decision if it is a sync-unrelated event irrelevant to execution of instructions. One of the processors except for the granted processor is selected as a master processor to be interrupted when a sync-unrelated event occurs. An interrupt generator supplies an interrupt to the request-granted processor when the first decision is made by the decoder or supplies it to the selected master processor if the second decision is made. When an event such as overvoltages and high temperatures occur during data transfer, the processor requesting such transfer is prevented from being indiscriminately interrupted.