Patents by Inventor Motoko Tanishima
Motoko Tanishima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140219035Abstract: Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data erase operation in all of the non-volatile memory circuits has been completed, the shift circuit outputs a continuous erase completion signal. Thereby, the data erase operation in all of the non-volatile memory circuits built in one chip can be continuously executed by one continuous erase command as is also the case where a single non-volatile memory circuit is built in.Type: ApplicationFiled: April 11, 2014Publication date: August 7, 2014Applicant: Spansion LLCInventor: Motoko TANISHIMA
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Patent number: 8717833Abstract: Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data erase operation in all of the non-volatile memory circuits has been completed, the shift circuit outputs a continuous erase completion signal. Thereby, the data erase operation in all of the non-volatile memory circuits built in one chip can be continuously executed by one continuous erase command as is also the case where a single non-volatile memory circuit is built in.Type: GrantFiled: April 23, 2008Date of Patent: May 6, 2014Assignee: Spansion LLCInventor: Motoko Tanishima
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Publication number: 20080205165Abstract: Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data erase operation in all of the non-volatile memory circuits has been completed, the shift circuit outputs a continuous erase completion signal. Thereby, the data erase operation in all of the non-volatile memory circuits built in one chip can be continuously executed by one continuous erase command as is also the case where a single non-volatile memory circuit is built in.Type: ApplicationFiled: April 23, 2008Publication date: August 28, 2008Applicant: Fujitsu LimitedInventor: Motoko TANISHIMA
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Patent number: 7372740Abstract: Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data erase operation in all of the non-volatile memory circuits has been completed, the shift circuit outputs a continuous erase completion signal. Thereby, the data erase operation in all of the non-volatile memory circuits built in one chip can be continuously executed by one continuous erase command as is also the case where a single non-volatile memory circuit is built in.Type: GrantFiled: May 11, 2005Date of Patent: May 13, 2008Assignee: Fujitsu LimitedInventor: Motoko Tanishima
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Patent number: 7149136Abstract: A memory circuit has a regular memory cell array; a redundant memory cell array that can replace a failed portion in the regular memory cell array; a redundant replacement memory for storing data on the failed portion in the regular memory cell array; and a pre-charge circuit disposed in the regular memory cell array, depending on the data on the failed portion, the failed portion in the regular memory cell array is replaced with the redundant memory cell array, whilst a pre-charge path is closed which leads to the pre-charge circuit corresponding to the failed portion. This enables a common redundant replacement memory to effect a relief of the failed portion and shutoff of the pre-charge current to the failed portion.Type: GrantFiled: December 1, 2005Date of Patent: December 12, 2006Assignee: Fujitsu LimitedInventors: Motoko Tanishima, Mitsuharu Sakakibara
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Publication number: 20060126397Abstract: Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data erase operation in all of the non-volatile memory circuits has been completed, the shift circuit outputs a continuous erase completion signal. Thereby, the data erase operation in all of the non-volatile memory circuits built in one chip can be continuously executed by one continuous erase command as is also the case where a single non-volatile memory circuit is built in.Type: ApplicationFiled: May 11, 2005Publication date: June 15, 2006Inventor: Motoko Tanishima
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Publication number: 20060083086Abstract: A memory circuit has a regular memory cell array; a redundant memory cell array that can replace a failed portion in the regular memory cell array; a redundant replacement memory for storing data on the failed portion in the regular memory cell array; and a pre-charge circuit disposed in the regular memory cell array, depending on the data on the failed portion, the failed portion in the regular memory cell array is replaced with the redundant memory cell array, whilst a pre-charge path is closed which leads to the pre-charge circuit corresponding to the failed portion. This enables a common redundant replacement memory to effect a relief of the failed portion and shutoff of the pre-charge current to the failed portion.Type: ApplicationFiled: December 1, 2005Publication date: April 20, 2006Inventors: Motoko Tanishima, Mitsuharu Sakakibara
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Patent number: 6999357Abstract: A memory circuit has a regular memory cell array; a redundant memory cell array that can replace a failed portion in the regular memory cell array; a redundant replacement memory for storing data on the failed portion in the regular memory cell array; and a pre-charge circuit disposed in the regular memory cell array, depending on the data on the failed portion, the failed portion in the regular memory cell array is replaced with the redundant memory cell array, whilst a pre-charge path is closed which leads to the pre-charge circuit corresponding to the failed portion. This enables a common redundant replacement memory to effect a relief of the failed portion and shutoff of the pre-charge current to the failed portion.Type: GrantFiled: August 5, 2003Date of Patent: February 14, 2006Assignee: Fujitsu LimitedInventors: Motoko Tanishima, Mitsuharu Sakakibara
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Publication number: 20040027880Abstract: A memory circuit has a regular memory cell array; a redundant memory cell array that can replace a failed portion in the regular memory cell array; a redundant replacement memory for storing data on the failed portion in the regular memory cell array; and a pre-charge circuit disposed in the regular memory cell array, depending on the data on the failed portion, the failed portion in the regular memory cell array is replaced with the redundant memory cell array, whilst a pre-charge path is closed which leads to the pre-charge circuit corresponding to the failed portion. This enables a common redundant replacement memory to effect a relief of the failed portion and shutoff of the pre-charge current to the failed portion.Type: ApplicationFiled: August 5, 2003Publication date: February 12, 2004Applicant: FUJITSU LIMITEDInventors: Motoko Tanishima, Mitsuharu Sakakibara
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Patent number: 6559691Abstract: An Nch-Tr having a gate connected to an input terminal and an Nch-Tr having a gate connected to an output signal voltage supply terminal through a Pch-Tr are connected to an output terminal for outputting an output signal carrying a second voltage level. In changing the output signal from a high level to a low level in accordance with a change of an input signal carrying a first voltage level, both the Nch-Trs are initially turned ON to lower the voltage of the output signal, and then the Nch-Tr having its gate connected to the output signal voltage supply terminal through the Pch-Tr is brought into a high ON state (a state of higher driving power) to turn the voltage of the output signal to the low level, so that the output signal can be changed quickly by a simple circuit configuration.Type: GrantFiled: October 1, 2001Date of Patent: May 6, 2003Assignee: Fujitsu LimitedInventors: Hiroshi Mawatari, Motoko Tanishima
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Publication number: 20020180494Abstract: An Nch-Tr having a gate connected to an input terminal and an Nch-Tr having a gate connected to an output signal voltage supply terminal through a Pch-Tr are connected to an output terminal for outputting an output signal carrying a second voltage level. In changing the output signal from a high level to a low level in accordance with a change of an input signal carrying a first voltage level, both the Nch-Trs are initially turned ON to lower the voltage of the output signal, and then the Nch-Tr having its gate connected to the output signal voltage supply terminal through the Pch-Tr is brought into a high ON state (a state of higher driving power) to turn the voltage of the output signal to the low level, so that the output signal can be changed quickly by a simple circuit configuration.Type: ApplicationFiled: October 1, 2001Publication date: December 5, 2002Applicant: FUJITSU LIMITEDInventors: Hiroshi Mawatari, Motoko Tanishima