Abstract: In a semiconductor memory cell array including word lines, bit lines, and a plurality of memory cells arranged at crossings between the word lines and the bit lines, the bit lines are grouped into odd and even numbered groups. A shift redundancy circuit is arranged between each group of odd or even bit lines and sense amplifier and write circuits for the purpose of shifting a defective memory cell to a redundant memory cell.

Abstract: A static RAM includes: a memory cell array including word lines, bit line pairs and memory cells; a row recorder; a column decoder; a DTD signal generator responsive to transition of input data or transition of a write enable signal for generating a data transition detection signal for a prescribed time period; and a write driver responsive to the write enable signal and the data transition detection signal for supplying the input data to a bit line pair selected by the column decoder. Even when there is a noise in write enable signal during reading cycle and data transition detection signal is generated erroneously, erroneous writing of data can be prevented, since write enable signal is not supplied to the write driver.

Abstract: A stable action of a memory cell in low voltage operation is realized, while assuring the reliability of the memory cell fined in structure for enhancing the degree of integration. An external supply voltage (V.sub.cc) is stepped down by a step-down transistor (Q1), and the stepped-down voltage is obtained as a potential for a bit line BIT. The external supply voltage (V.sub.cc) is also stepped down by a step-down transistor (Q5), and the stepped-down voltage is obtained as a potential for a bit line BIT. Furthermore, the external supply voltage (V.sub.cc) is stepped down by a step-down transistor (Q3), and the stepped-down voltage is obtained as an internal supply voltage for a memory cell (MC). On the contrary, to gate electrodes of both access transistors A1, A2, the external supply voltage V.sub.cc is directly applied through word drivers 1, 2, respectively.

Abstract: Bit lines which are adjacent to each other are connected to bit line signal input/output lines which are not adjacent to each other, via through holes. By this connection, data input/output lines, shield lines and a global word line are arranged between the through holes, whereby the distance between the through holes can be widened, minimum space between the bit lines can be widened, and therefore, higher integration of the memory array is realized.

Abstract: In a memory cell array, memory cells are formed in a matrix. Bit lines are formed to be connected to prescribed memory cells. Emitters of bipolar transistors are connected to bit lines. Bipolar transistors have their bases connected to each other, and further to precharge signal control means. Collector regions of bipolar transistors are connected to a power supply node. Bipolar transistors have a base region formed by introducing a p type impurity to the entire main surface of the semiconductor substrate, and n type impurity concentration included in the collector region immediately below the base region is at most 5.times.10.sup.18 cm.sup.-1. Consequently, a semiconductor memory device having a bipolar transistor which is capable of high speed operation and having high reliability can be manufactured at low cost.

Abstract: A semiconductor memory device changeable in word organization has a plurality of input/output terminals and a plurality of input terminals. Each of the plurality of input/output terminals and the plurality of input terminals are connected to an internal circuit via input/output buffers. These input/output buffers have identical structures and arrangements with identical input/output capacitance. The output buffer in the input/output buffer connected to an input terminal is coupled to a predetermined potential. The output buffer in the input/output buffer connected to an input/output terminal is activated by an output driver. The semiconductor memory device is generally set to a 1M word.times.1 bit organization. This semiconductor memory device may be set to a 256 k word.times.4 bit organization at the time of testing.