Patents by Inventor Motonobu Nagafuji

Motonobu Nagafuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4897801
    Abstract: In a display terminal equipment, a display device and a plurality of input devices are connected to a controller. Each input device is operated by an operator for inputting information. The controller controls the information entered from a different input device to be displayed on a different display area of the display device. It becomes possible for a plurality of operators to share a single display device and a single display terminal equipment while handling his or her own input device at the same time.
    Type: Grant
    Filed: August 17, 1987
    Date of Patent: January 30, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiharu Kazama, Motonobu Nagafuji
  • Patent number: 4677582
    Abstract: An operation processing apparatus executes an instruction accompanied by addition/subtraction for one word and halfword operands at a high speed. An expander expands the sign of a second operand in its upper halfword bits to produce an expanded second operand having the same length as that of a first operand. An arithmetic unit operates the first operand and the expanded second operand.
    Type: Grant
    Filed: April 14, 1983
    Date of Patent: June 30, 1987
    Assignee: Hitachi, Ltd.
    Inventor: Motonobu Nagafuji
  • Patent number: 4542476
    Abstract: An arithmetic logic unit processes a variable operand length instruction such as a decimal arithmetic operation instruction, a plurality of bytes at a time using a multi-byte depth arithmetic operation unit. Multi-byte data including first and second operands are supplied to the arithmetic logic unit through a suppressing circuit. The suppressing circuit suppresses unnecessary bytes other than operand bytes and suppresses all of the bytes of one of the operands when the one operand has been exhausted.
    Type: Grant
    Filed: August 3, 1982
    Date of Patent: September 17, 1985
    Assignee: Hitachi, Ltd.
    Inventor: Motonobu Nagafuji
  • Patent number: 4456955
    Abstract: A data processing system has an arithmetic operating unit to process a plurality of bytes at a time and carries out an arithmetic operation on first and second operands each starting from any desired address on a main memory and having any desired number of byte length. The second operand is aligned to an operand position of the first operand and the aligned second operand is supplied to the operating unit while the first operand is supplied as it is to the operating unit. Since the second operand is aligned to the operand position of the first operand before it is processed in the operating unit, the number of times of alignment is reduced.
    Type: Grant
    Filed: August 18, 1981
    Date of Patent: June 26, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Tomoatsu Yanagita, Motonobu Nagafuji