Abstract: A clock signal, a data signal, and a latch signal are commonly supplied from a controller to a plurality of the data drivers. The data signal and the latch signal are synchronized with the clock signal. In each of the data drivers, an internal latch signal is generated in synchronization with the clock signal in response to the latch signal. Timing of a rising edge of the internal latch signal is independently controlled in each data driver in accordance with position information where each data driver is arranged.

Abstract: The present invention provides a liquid-crystal display device that is able to reduce EMI, current consumption, and so forth in an interchip transfer of display data, a timing signal, and so forth and to provide an appropriate timing margin. In an interchip transfer of display data, a timing signal, and so forth that uses a plurality of data drivers, a certain data driver is used as a data driver. When the data driver is used in a first stage, an internal receiver is made to function as an RSDS receiver by fixing the IFM terminal at the “H” level. The received RSDS signal constitutes a CMOS signal that has been divided into two by the receiver and is output by the transmitter. Here, a data inversion signal is generated and output by the transmitter. When the data driver is used in the second or subsequent stage, the internal receiver is made to function as a CMOS receiver by fixing the IFM terminal at the “L” level.

Abstract: To reduce EMI and current consumption in internal wiring after display data have been input to a data driver. Display data DN/DP constituted by RSDS signals input to a data driver in a first stage are converted to display data DA constituted by CMOS signals, subjected to primary inversion control according to a data inversion signal INV generated inside, and transferred into internal wiring 31 in a data capturing circuit 30. Then, the display data are subjected to secondary inversion control by a secondary data inversion circuit 33 disposed immediately before data registers 34 according to the data inversion signal INV, and then captured by the data registers 34. Further, chip-to-chip transfer of the display data DA and the data inversion signal INV to the data drivers in second and subsequent stages is performed through the internal wiring 31 and internal wiring 32. Then, as in the data driver in the first stage, the display data DA are captured by the data registers 34.

Abstract: A liquid crystal display driver includes: a positive polarity amplifier; a negative polarity amplifier; and a determining part. The positive polarity amplifier is supplied with a first power source voltage and a second power source voltage, and amplifies a decoded first video data to output as a first data signal. The negative polarity amplifier is supplied with a third power source voltage and a fourth power source voltage, and amplifies a decoded second video data to output as a second data signal. The determining part determines whether an operation is a Half-VDD operation or a Full-VDD operation based on one of a comparison result between the second power source voltage and a first reference voltage and a comparison result between the fourth power source voltage and a second reference voltage to output a determination signal.

Abstract: A driver includes a gradation voltage supplying section configured to supply a first output gradation voltage to a data line in a first display period; and a charge share performing section configured to supply a second voltage between the first output gradation voltage and a first voltage to the data line in a charge share period after the first display period. The first voltage is a common voltage between the first output gradation voltage and a second output gradation voltage of a polarity opposite to that of the first output gradation voltage.

Abstract: To reduce EMI and current consumption in internal wiring after display data have been input to a data driver. Display data DN/DP constituted by RSDS signals input to a data driver in a first stage are converted to display data DA constituted by CMOS signals, subjected to primary inversion control according to a data inversion signal INV generated inside, and transferred into internal wiring 31 in a data capturing circuit 30. Then, the display data are subjected to secondary inversion control by a secondary data inversion circuit 33 disposed immediately before data registers 34 according to the data inversion signal INV, and then captured by the data registers 34. Further, chip-to-chip transfer of the display data DA and the data inversion signal INV to the data drivers in second and subsequent stages is performed through the internal wiring 31 and internal wiring 32. Then, as in the data driver in the first stage, the display data DA are captured by the data registers 34.

Abstract: A clock signal, a data signal, and a latch signal are commonly supplied from a controller to a plurality of the data drivers. The data signal and the latch signal are synchronized with the clock signal. In each of the data drivers, an internal latch signal is generated in synchronization with the clock signal in response to the latch signal. Timing of a rising edge of the internal latch signal is independently controlled in each data driver in accordance with position information where each data driver is arranged.

Abstract: To reduce EMI and current consumption in internal wiring after display data have been input to a data driver. Display data DN/DP constituted by RSDS signals input to a data driver in a first stage are converted to display data DA constituted by CMOS signals, subjected to primary inversion control according to a data inversion signal INV generated inside, and transferred into internal wiring 31 in a data capturing circuit 30. Then, the display data are subjected to secondary inversion control by a secondary data inversion circuit 33 disposed immediately before data registers 34 according to the data inversion signal INV, and then captured by the data registers 34. Further, chip-to-chip transfer of the display data DA and the data inversion signal INV to the data drivers in second and subsequent stages is performed through the internal wiring 31 and internal wiring 32. Then, as in the data driver in the first stage, the display data DA are captured by the data registers 34.

Abstract: The present invention provides a liquid-crystal display device that is able to reduce EMI, current consumption, and so forth in an interchip transfer of display data, a timing signal, and so forth and to provide an appropriate timing margin. In an interchip transfer of display data, a timing signal, and so forth that uses a plurality of data drivers, a certain data driver is used as a data driver. When the data driver is used in a first stage, an internal receiver is made to function as an RSDS receiver by fixing the IFM terminal at the “H” level. The received RSDS signal constitutes a CMOS signal that has been divided into two by the receiver and is output by the transmitter. Here, a data inversion signal is generated and output by the transmitter. When the data driver is used in the second or subsequent stage, the internal receiver is made to function as a CMOS receiver by fixing the IFM terminal at the “L” level.

Abstract: To reduce EMI and current consumption in internal wiring after display data have been input to a data driver. Display data DN/DP constituted by RSDS signals input to a data driver in a first stage are converted to display data DA constituted by CMOS signals, subjected to primary inversion control according to a data inversion signal INV generated inside, and transferred into internal wiring 31 in a data capturing circuit 30. Then, the display data are subjected to secondary inversion control by a secondary data inversion circuit 33 disposed immediately before data registers 34 according to the data inversion signal INV, and then captured by the data registers 34. Further, chip-to-chip transfer of the display data DA and the data inversion signal INV to the data drivers in second and subsequent stages is performed through the internal wiring 31 and internal wiring 32. Then, as in the data driver in the first stage, the display data DA are captured by the data registers 34.

Abstract: The output circuit is provided with an operational amplifier, a current supply circuit and an impedance changing circuit. The current supply circuit supplies current to the operational amplifiers at rising and falling of an output signal delivered by the operational amplifier. The impedance changing circuit changes the impedance between the operational amplifier and an output terminal.