Patents by Inventor Motoo Tanaka

Motoo Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7571200
    Abstract: A seedable pseudo-random number generator. A linear feedback shift register (LFSR) arrangement is used to generate a first pseudo-random number, and a cellular automata is used to generate a second pseudo-random number. The bits of the LFSR arrangement are XORed with bits of the cellular automata to generate the output pseudo-random number.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: August 4, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: J. Barry Shackleford, Richard J. Carter, Motoo Tanaka
  • Patent number: 7043730
    Abstract: A system and method is disclosed for network resource management. The method discloses: receiving a request to execute a task; calculating a virtual set of resources required to execute the task; reserving a set of network services for each virtual resource; and executing the task on the reserved services The system discloses means of implementing the method.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: May 9, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Motoo Tanaka
  • Patent number: 6990507
    Abstract: The present invention provides a method and apparatus to check the arithmetic increment function through prediction of the change in the bit-level parity of the result by means of a series of identical cells connected in a linear array. The array predicts the change in parity produced by the arithmetic increment function which allows the increment function to be checked in an efficient manner. The advantages of the present invention are that the parity check design saves hardware cost over prior schemes that require duplication of incrementers and comparison of the results and schemes that require generation of parity after incrementing, and that the iterative, identical cell implementation of the parity predictor is well-suited for current VLSI and future digital logic circuits as they progress towards molecular, self-assembling components.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: January 24, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: J. Barry Shackleford, Motoo Tanaka
  • Patent number: 6985918
    Abstract: A system and a method to generate cellular automata based random number generators (CA-based RNGs) are presented A CA-based RNG is where an output of each cell of the CA at time t is dependent on inputs from any cells of the CA (including perhaps itself) at time t?1. The connections (or inputs) are selected to produce high entropy such that the RNG passes a standard suite of random number of tests, such as the DIEHARD suite. The RNGs may be implemented with field programmable gate arrays.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: January 10, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: J. Barry Shackleford, Motoo Tanaka
  • Patent number: 6952767
    Abstract: A system and method for maintaining a computer system at a predetermined cost/performance level by automatically selecting hardware and software upgrades for a given, desired level of technology and cost. A subscriber to the inventive system either has an existing computer system or selects a standard computer configuration from an available list provided through the system. The subscriber also selects a desired class of computer technology that is a function of the cost and performance level of the hardware and software components that are available to configure the computer system. Information related to any changes in technology performance and cost for computer system components is input to the system. This information is assessed by the system, and periodically various components of the subscriber's computer system are upgraded to maximize the performance of the computer system while keeping it within the cost/performance ratio of the class or level of technology selected by the subscriber.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: October 4, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Motoo Tanaka
  • Patent number: 6910057
    Abstract: A system and a method to reduce a search space to determine viable cellular automata based random number generators (CA-based RNGs) are presented. A CA-based RNG is where an output of each cell of the CA at time t is dependent on inputs from any cells of the CA (including perhaps itself) at time t?1. The connections (or inputs) are selected to produce high entropy such that the RNG passes a standard suite of random number of tests, such as the DIEHARD suite. As the number of inputs grow (corresponding to the neighborhood size), the number of truth tables grows dramatically. By reducing the search space of viable CA-based RNGs, high quality random number generators with higher neighborhood sizes may be found.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: June 21, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: J. Barry Shackleford, Motoo Tanaka
  • Publication number: 20050086007
    Abstract: A method and apparatus is used to discover elements in a compound with a fitness function by receiving a set of monoisotopic mass look-up-tables (LUTs), identifying mass values in parallel by cross-referencing monoisotopic mass LUT addresses, evaluating different permutations of the identified mass values, accessing values in mass spectroscopy data sets according to the permutations of mass values and determining the combination of elements in the compound according to a correlation between the permutations of mass values and the mass values associated with the mass spectroscopy data set.
    Type: Application
    Filed: October 16, 2003
    Publication date: April 21, 2005
    Inventors: J. Shackleford, Motoo Tanaka
  • Patent number: 6832303
    Abstract: A method and system are disclosed for managing an allocation of a portion of a memory associated with a central processing unit system that can be selectively coupled to a bus of the central processing unit system. In accordance with exemplary embodiments of the present invention, a first portion of the memory is allocated for a first range of addresses. The allocated first portion of the memory is selectively coupled to the bus of the central processing unit system. The selectively coupled first portion of the memory is decoupled from the bus of the central processing unit system. The decoupled first portion of the memory is reallocated for a second range of addresses.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: December 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Motoo Tanaka
  • Publication number: 20040215922
    Abstract: A method and apparatus is used select a multiplication constant for addressing a storage location with reduced processing requirements. The selection includes receiving a multiplication constant for use in an arithmetic operation to address a storage location, determining an upper limit multiplication constant compared with the received multiplication constant, counting the number of zero digits for each binary value contained in the range of binary values greater than the multiplication constant value and less than or equal to the upper limit multiplication constant and selecting the binary value from the range having the greatest number of zero digits as the modified multiplication constant.
    Type: Application
    Filed: April 24, 2003
    Publication date: October 28, 2004
    Inventors: J. Barry Shackleford, Motoo Tanaka
  • Publication number: 20040210399
    Abstract: A method and apparatus is used to initialize a population memory of electronic chromosomes for use in genetic algorithm (GA) analysis. Initializing the population memory includes providing an initial state into a first parent chromosome and a second parent chromosome, entering a current state of a first parent chromosome and a second parent chromosome into a cellular automata, selecting a neighbor state of the second parent chromosome for entry into the cellular automata, and generating a random number sequence using the cellular automata for use in the population memory.
    Type: Application
    Filed: April 15, 2003
    Publication date: October 21, 2004
    Inventors: J. Barry Shackleford, Motoo Tanaka
  • Publication number: 20040162794
    Abstract: A method and apparatus is used to organize aspects of electronic chromosomes for use in genetic algorithm (GA) analysis. The organization operations include receiving one or more elements for composing into an electronic chromosome analyzed using a genetic algorithm, ordering each of the one or more elements into an element sequence as determined by a fitness function, selecting a binary number sequence having a single-bit difference between each pair of adjacent binary numbers, and sequentially associating each of the one or more elements in the element sequence with a binary number in accordance with the binary number sequence.
    Type: Application
    Filed: February 14, 2003
    Publication date: August 19, 2004
    Inventors: J. Barry Shackleford, Motoo Tanaka
  • Patent number: 6723982
    Abstract: A method and apparatus reduces storage requirements for identifying a sequence of elements in a compound. The storage reduction receives a set of monoisotopic masses designed to address entries from two or more mass spectroscopy data sets according to a fitness function, analyzes the fitness function configured to facilitate identification of a sequence of elements in the compound, determines a minimum address range for addressing entries in each of the two or more mass spectroscopy data sets according to sequence of elements and fitness function analysis and reduces the size of at least one of the two or more mass spectroscopy data sets to selected mass data values according to the minimum address range.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: April 20, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: J. Barry Shackleford, Motoo Tanaka
  • Publication number: 20040054562
    Abstract: A system and method is disclosed for enterprise information management. The method of the present invention discloses: completing a set of fields within a uniformly formatted employee work record; partitioning the employee work record by project into a set of project specific work records; selecting a subset of the project specific employee work records using a predetermined set of filtering criteria; and generating an enterprise report from the selected subset of work records. The method also discloses: completing a set of fields within a uniformly formatted project work record having a uniform format; partitioning the project work record by employee into a set of employee specific work records; selecting a subset of the employee specific employee work records using a predetermined set of filtering criteria; and generating an enterprise report from the selected subset of work records. The system discloses some means for effecting the method.
    Type: Application
    Filed: September 16, 2002
    Publication date: March 18, 2004
    Inventor: Motoo Tanaka
  • Publication number: 20040044769
    Abstract: A system and method is disclosed for network resource management.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 4, 2004
    Inventor: Motoo Tanaka
  • Publication number: 20030220955
    Abstract: The present invention provides a method and apparatus to check the arithmetic increment function through prediction of the change in the bit-level parity of the result by means of a series of identical cells connected in a linear array. The array predicts the change in parity produced by the arithmetic increment function which allows the increment function to be checked in an efficient manner. The advantages of the present invention are that the parity check design saves hardware cost over prior schemes that require duplication of incrementers and comparison of the results and schemes that require generation of parity after incrementing, and that the iterative, identical cell implementation of the parity predictor is well-suited for current VLSI and future digital logic circuits as they progress towards molecular, self-assembling components.
    Type: Application
    Filed: May 21, 2002
    Publication date: November 27, 2003
    Inventors: J. Barry Shackleford, Motoo Tanaka
  • Publication number: 20030204541
    Abstract: A seedable pseudo-random number generator. A linear feedback shift register (LFSR) arrangement is used to generate a first pseudo-random number, and a cellular automata is used to generate a second pseudo-random number. The bits of the LFSR arrangement are XORed with bits of the cellular automata to generate the output pseudo-random number.
    Type: Application
    Filed: April 24, 2002
    Publication date: October 30, 2003
    Applicant: Hewlett Packard Company
    Inventors: J. Barry Shackleford, Richard J. Carter, Motoo Tanaka
  • Publication number: 20030126393
    Abstract: A method and system are disclosed for managing an allocation of a portion of a memory associated with a central processing unit system that can be selectively coupled to a bus of the central processing unit system. In accordance with exemplary embodiments of the present invention, a first portion of the memory is allocated for a first range of addresses. The allocated first portion of the memory is selectively coupled to the bus of the central processing unit system. The selectively coupled first portion of the memory is decoupled from the bus of the central processing unit system. The decoupled first portion of the memory is reallocated for a second range of addresses.
    Type: Application
    Filed: January 3, 2002
    Publication date: July 3, 2003
    Inventor: Motoo Tanaka
  • Publication number: 20030097387
    Abstract: A system and a method to reduce a search space to determine viable cellular automata based random number generators (CA-based RNGs) are presented. A CA-based RNG is where an output of each cell of the CA at time t is dependent on inputs from any cells of the CA (including perhaps itself) at time t−1. The connections (or inputs) are selected to produce high entropy such that the RNG passes a standard suite of random number of tests, such as the DIEHARD suite. As the number of inputs grow (corresponding to the neighborhood size), the number of truth tables grows dramatically. By reducing the search space of viable CA-based RNGs, high quality random number generators with higher neighborhood sizes may be found.
    Type: Application
    Filed: October 17, 2001
    Publication date: May 22, 2003
    Inventors: J. Barry Shackleford, Motoo Tanaka
  • Publication number: 20030078951
    Abstract: A system and a method to generate cellular automata based random number generators (CA-based RNGs) are presented A CA-based RNG is where an output of each cell of the CA at time t is dependent on inputs from any cells of the CA (including perhaps itself) at time t−1. The connections (or inputs) are selected to produce high entropy such that the RNG passes a standard suite of random number of tests, such as the DIEHARD suite. The RNGs may be implemented with field programmable gate arrays.
    Type: Application
    Filed: October 17, 2001
    Publication date: April 24, 2003
    Inventors: J. Barry Shackleford, Motoo Tanaka
  • Publication number: 20030076956
    Abstract: System and method to emulate cellular automata based random number generators (CA-based RNGs) in software are presented. Also, system and method to automatically generate software emulators of CA-based RNG are presented. A CA-based RNG is where an output of each cell of the CA at time t is dependent on inputs from any cells of the CA (including perhaps itself) at time t−1. The simulation software are high performing due to parallel simulation of multiple cells of the CA rather than emulating behaviors of cells individually and then combining the results. The simulation software may also include parallel site spacing capabilities.
    Type: Application
    Filed: October 17, 2001
    Publication date: April 24, 2003
    Inventors: J. Barry Shackleford, Motoo Tanaka