Patents by Inventor Motoru YOSHIDA
Motoru YOSHIDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11830795Abstract: A semiconductor device includes a base plate, a substrate, a semiconductor element, a case, and a wiring terminal. The case is disposed on the base plate so as to cover the substrate and the semiconductor element. The wiring terminal is electrically connected to the semiconductor element. The case includes a first case unit and a second case unit that is separate from the first case unit. The wiring terminal includes a first wiring unit and a second wiring unit. The first wiring unit is disposed so as to protrude from an inside to an outside of the case, and is electrically connected to the semiconductor element. The second wiring unit is bent with respect to the first wiring unit and disposed outside the case. The first case unit and the second case unit are disposed so as to sandwich the first wiring unit.Type: GrantFiled: July 4, 2019Date of Patent: November 28, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yuji Sato, Yoshinori Yokoyama, Motoru Yoshida, Jun Fujita
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Publication number: 20230290874Abstract: A method of manufacturing a silicon carbide semiconductor device includes a step of forming gate trench, a step of forming Schottky trench, a step of forming a silicon oxide film in the gate trench and the Schottky trench, a step of forming a polycrystalline silicon film inside the silicon oxide film, a step of etching back the polycrystalline silicon film, a step of forming an interlayer insulating film on a gate electrode in the gate trench, a step of removing, by wet etching, the polycrystalline silicon film in the Schottky trench after opening a hole in the interlayer insulating film, a step of forming an ohmic electrode on a source region, a step of removing the silicon oxide film in the Schottky trench, and a step of forming a source electrode in the Schottky trench, which is in Schottky junction with a drift layer.Type: ApplicationFiled: September 30, 2020Publication date: September 14, 2023Applicant: Mitsubishi Electric CorporationInventors: Motoru YOSHIDA, Rina TANAKA, Yutaka FUKUI, Hideyuki HATTA
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Publication number: 20230215942Abstract: A semiconductor device according to the present disclosure includes: a gate electrode provided in a gate trench and provided so as to oppose a source region via a gate insulating film; a first bottom protection region of a second conductivity type provided below the gate insulating film; a plurality of first connection regions of the second conductivity type provided at a first interval in an extension direction of the gate trench and electrically connecting the first bottom protection region and a body region; a Schottky electrode provided in a Schottky trench; a second bottom protection region of the second conductivity type provided below the Schottky electrode; and a plurality of second connection regions of the second conductivity type provided at a second interval smaller than the first interval in an extension direction of the Schottky trench and electrically connecting the second bottom protection region and the body region.Type: ApplicationFiled: August 25, 2020Publication date: July 6, 2023Applicant: Mitsubishi Electric CorporationInventors: Rina TANAKA, Hideyuki HATTA, Motoru YOSHIDA, Yutaka FUKUI, Shiro HINO
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Publication number: 20230047789Abstract: Provided is a semiconductor device capable of suppressing an Al slide at a time of an operation under a high temperature in a laminated structure of an aluminum electrode layer and a copper electrode layer. Accordingly, in the semiconductor device according to the present disclosure, a first copper electrode layer includes a plurality of protruding regions as regions protruding toward the aluminum electrode layer in an interface with the aluminum electrode layer.Type: ApplicationFiled: April 6, 2020Publication date: February 16, 2023Applicant: Mitsubishi Electric CorporationInventors: Motoru YOSHIDA, Yuji SATO, Kazuyuki SUGAHARA
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Publication number: 20220230945Abstract: A semiconductor device includes a base plate, a substrate, a semiconductor element, a case, and a wiring terminal. The case is disposed on the base plate so as to cover the substrate and the semiconductor element. The wiring terminal is electrically connected to the semiconductor element. The case includes a first case unit and a second case unit that is separate from the first case unit. The wiring terminal includes a first wiring unit and a second wiring unit. The first wiring unit is disposed so as to protrude from an inside to an outside of the case, and is electrically connected to the semiconductor element. The second wiring unit is bent with respect to the first wiring unit and disposed outside the case. The first case unit and the second case unit are disposed so as to sandwich the first wiring unit.Type: ApplicationFiled: July 4, 2019Publication date: July 21, 2022Applicant: Mitsubishi Electric CorporationInventors: Yuji SATO, Yoshinori YOKOYAMA, Motoru YOSHIDA, Jun FUJITA
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Patent number: 11195803Abstract: An object is to provide a technique capable of suppressing a corrosion of a first electrode and a second electrode. A semiconductor element includes a semiconductor substrate, an Al electrode, a polyimide member selectively disposed on the Al electrode, and an Ni electrode. The polyimide member includes a protruding part which protrudes in a plane direction of an upper surface of the Al electrode and which has a lower portion having contact with the Al electrode in a cross-sectional view, in at least part of a peripheral part of the polyimide member in a top view. The Ni electrode is disposed on the Al electrode and the protruding part.Type: GrantFiled: March 8, 2018Date of Patent: December 7, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Motoru Yoshida, Jun Fujita, Yuji Sato
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Patent number: 11158511Abstract: A semiconductor device that includes a semiconductor layer disposed on a semiconductor substrate, a first semiconductor region provided in an upper layer portion of the semiconductor layer, a second semiconductor region provided in an upper layer portion of the first semiconductor region, a gate insulation film, a gate electrode, a first main electrode that is provided on an interlayer insulation film that covers the gate electrode and that is electrically connected to the second semiconductor region via a contact hole, and a second main electrode disposed on a second main surface of the semiconductor substrate. The first main electrode includes an underlying electrode film connected to the second semiconductor region via the contact hole, and a copper film provided on the underlying electrode film. The copper film includes at least a portion that serves as a stress relaxation layer having a smaller grain size than the other portion of the copper film.Type: GrantFiled: February 2, 2017Date of Patent: October 26, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Kazuyuki Sugahara, Hiroaki Okabe, Motoru Yoshida
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Publication number: 20200395314Abstract: An object is to provide a technique capable of suppressing a corrosion of a first electrode and a second electrode. A semiconductor element includes a semiconductor substrate, an Al electrode, a polyimide member selectively disposed on the Al electrode, and an Ni electrode. The polyimide member includes a protruding part which protrudes in a plane direction of an upper surface of the Al electrode and which has a lower portion having contact with the Al electrode in a cross-sectional view, in at least part of a peripheral part of the polyimide member in a top view. The Ni electrode is disposed on the Al electrode and the protruding part.Type: ApplicationFiled: March 8, 2018Publication date: December 17, 2020Applicant: Mitsubishi Electric CorporationInventors: Motoru YOSHIDA, Jun FUJITA, Yuji SATO
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Publication number: 20200273716Abstract: A semiconductor device is provided that can minimize the occurrence of poor joining between a copper electrode and a copper wire. The semiconductor device includes a semiconductor substrate; a copper electrode layer formed on the semiconductor substrate; a metallic thin-film layer formed on the copper electrode layer for preventing oxidation of the copper electrode layer, the metallic thin-film layer having an opening through which the copper electrode layer is exposed, the opening being located on an inner side relative to an outer periphery of the metallic thin-film layer; and an interconnection member containing copper as a main component, the interconnection member including a joining region covering the opening, the interconnection member being joined to the metallic thin-film layer and joined to the copper electrode layer in the opening.Type: ApplicationFiled: April 12, 2018Publication date: August 27, 2020Applicant: Mitsubishi Electric CorporationInventors: Yuji SATO, Tsuyoshi URAJI, Jun FUJITA, Motoru YOSHIDA
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Patent number: 10707146Abstract: Provided is a semiconductor device having high heat conductivity and high productivity. A semiconductor device includes an insulating substrate, a semiconductor element, a die-bond material, a joining material, and a cooler. The insulating substrate has an insulating ceramic, a first conductive plates disposed on one surface of the insulating ceramic, and a second conductive plate disposed on another surface of the insulating ceramic. The semiconductor element is disposed on the first conductive plate through the die-bond material. The die-bond material contains sintered metal. The semiconductor element has a bending strength degree of 700 MPa or more, and has a thickness of 0.05 mm or more and 0.1 mm or less. The cooler is joined to the second conductive plate through the joining material.Type: GrantFiled: October 31, 2016Date of Patent: July 7, 2020Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Motoru Yoshida, Yoshiyuki Suehiro, Kazuyuki Sugahara, Yosuke Nakanishi, Yoshinori Yokoyama, Shinnosuke Soda, Komei Hayashi
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Patent number: 10697078Abstract: A method of forming Cu plating of the present invention includes: a first step of forming a Cu seed layer on one of surfaces of a substrate such that an average grain size is 50 nm or more and 300 nm or less; a second step of forming an oxide film on a surface of the Cu seed layer in an oxygen atmosphere; a third step of removing a part of the oxide film; and a fourth step of feeding power to the Cu seed layer to form Cu plating on a surface of the oxide film on the Cu seed layer by electrolytic plating.Type: GrantFiled: November 12, 2015Date of Patent: June 30, 2020Assignee: Mitsubishi Electric CorporationInventors: Yuji Sato, Jun Fujita, Motoru Yoshida, Kazuyo Endo
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Patent number: 10529587Abstract: A semiconductor device includes a semiconductor substrate, an insulating film, and an electrode. The semiconductor substrate includes a first surface. The insulating film is provided on the first surface of the semiconductor substrate and includes a second surface opposite to the first surface. The electrode is connected to the second surface of the insulating film and includes a side surface, a first face in contact with the insulating film, and a second face opposite to the first face. An outer periphery of the second face of the electrode is formed on an inner side of an outer periphery of the first face.Type: GrantFiled: May 15, 2017Date of Patent: January 7, 2020Assignee: Mitsubishi Electric CorporationInventors: Yuji Sato, Motoru Yoshida, Jun Fujita
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Publication number: 20190148163Abstract: A semiconductor device includes a semiconductor substrate, an insulating film, and an electrode. The semiconductor substrate includes a first surface. The insulating film is provided on the first surface of the semiconductor substrate and includes a second surface opposite to the first surface. The electrode is connected to the second surface of the insulating film and includes a side surface, a first face in contact with the insulating film, and a second face opposite to the first face. An outer periphery of the second face of the electrode is formed on an inner side of an outer periphery of the first face.Type: ApplicationFiled: May 15, 2017Publication date: May 16, 2019Applicant: Mitsubishi Electric CorporationInventors: Yuji SATO, Motoru YOSHIDA, Jun FUJITA
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Patent number: 10276502Abstract: A method for manufacturing a semiconductor device includes: a process of forming a Cu wiring electrode by a plating method above a semiconductor element using a wide bandgap semiconductor as a base material; a reducing process of reducing the Cu wiring electrode under a NH3 atmosphere; a heating process of heating the Cu wiring electrode at the same time as the reducing process; a process of forming a diffusion prevention film covering the Cu wiring electrode after the heating process; and a sealing process of covering the diffusion prevention film with an organic resin film.Type: GrantFiled: November 27, 2015Date of Patent: April 30, 2019Assignee: Mitsubishi Electric CorporationInventors: Motoru Yoshida, Hiroaki Okabe, Kazuyuki Sugahara
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Publication number: 20190122955Abstract: Provided is a semiconductor device having high heat conductivity and high productivity. A semiconductor device includes an insulating substrate, a semiconductor element, a die-bond material, a joining material, and a cooler. The insulating substrate has an insulating ceramic, a first conductive plates disposed on one surface of the insulating ceramic, and a second conductive plate disposed on another surface of the insulating ceramic. The semiconductor element is disposed on the first conductive plate through the die-bond material. The die-bond material contains sintered metal. The semiconductor element has a bending strength degree of 700 MPa or more, and has a thickness of 0.05 mm or more and 0.1 mm or less. The cooler is joined to the second conductive plate through the joining material.Type: ApplicationFiled: October 31, 2016Publication date: April 25, 2019Applicant: Mitsubishi Electric CorporationInventors: Motoru YOSHIDA, Yoshiyuki SUEHIRO, Kazuyuki SUGAHARA, Yosuke NAKANISHI, Yoshinori YOKOYAMA, Shinnosuke SODA, Komei HAYASHI
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Publication number: 20190062938Abstract: A method of forming Cu plating of the present invention includes: a first step of forming a Cu seed layer on one of surfaces of a substrate such that an average grain size is 50 nm or more and 300 nm or less; a second step of forming an oxide film on a surface of the Cu seed layer in an oxygen atmosphere; a third step of removing a part of the oxide film; and a fourth step of feeding power to the Cu seed layer to form Cu plating on a surface of the oxide film on the Cu seed layer by electrolytic plating.Type: ApplicationFiled: November 12, 2015Publication date: February 28, 2019Applicant: Mitsubishi Electric CorporationInventors: Yuji SATO, Jun FUJITA, Motoru YOSHIDA, Kazuyo ENDO
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Publication number: 20190057873Abstract: A semiconductor device that includes a semiconductor layer disposed on a semiconductor substrate, a first semiconductor region provided in an upper layer portion of the semiconductor layer, a second semiconductor region provided in an upper layer portion of the first semiconductor region, a gate insulation film, a gate electrode, a first main electrode that is provided on an interlayer insulation film that covers the gate electrode and that is electrically connected to the second semiconductor region via a contact hole, and a second main electrode disposed on a second main surface of the semiconductor substrate. The first main electrode includes an underlying electrode film connected to the second semiconductor region via the contact hole, and a copper film provided on the underlying electrode film. The copper film includes at least a portion that serves as a stress relaxation layer having a smaller grain size than the other portion of the copper film.Type: ApplicationFiled: February 2, 2017Publication date: February 21, 2019Applicant: Mitsubishi Electric CorporationInventors: Kazuyuki SUGAHARA, Hiroaki OKABE, Motoru YOSHIDA
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Publication number: 20180040563Abstract: A method for manufacturing a semiconductor device includes: a process of forming a Cu wiring electrode by a plating method above a semiconductor element using a wide bandgap semiconductor as a base material; a reducing process of reducing the Cu wiring electrode under a NH3 atmosphere; a heating process of heating the Cu wiring electrode at the same time as the reducing process; a process of forming a diffusion prevention film covering the Cu wiring electrode after the heating process; and a sealing process of covering the diffusion prevention film with an organic resin film.Type: ApplicationFiled: November 27, 2015Publication date: February 8, 2018Applicant: Mitsubishi Electric CorporationInventors: Motoru YOSHIDA, Hiroaki OKABE, Kazuyuki SUGAHARA
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Patent number: 9842738Abstract: A method of manufacturing a silicon carbide semiconductor device is provided. The method suppresses the increase in the number of manufacturing steps and is capable of suppressing the degradation of ohmic characteristics of an alloy layer with respect to a semiconductor substrate. The method includes a step of forming a metal layer made of a first metal on a semiconductor substrate made of silicon carbide; a step of forming a metal nitride film obtained by nitriding a second metal on the metal layer; a step of directing a laser light through the metal nitride film to form a layer of an alloy of silicon carbide in the semiconductor substrate and the first metal in the metal layer; and a step of forming an electrode on the metal nitride film.Type: GrantFiled: April 9, 2014Date of Patent: December 12, 2017Assignee: Mitsubishi Electric CorporationInventors: Yosuke Nakanishi, Hiroaki Okabe, Motoru Yoshida, Kazuyuki Sugahara, Takaaki Tominaga
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Patent number: 9721915Abstract: A semiconductor device capable of inhibiting oxidation of a Cu wiring even in a high temperature operation. The semiconductor device includes a semiconductor substrate having a main surface, a Cu electrode which is selectively formed on a side of the main surface of the semiconductor substrate, an antioxidant film formed on an upper surface of the Cu electrode except an end portion thereof, an organic resin film which is formed on the main surface of the semiconductor substrate and covers a side surface of the Cu electrode and the end portion of the upper surface thereof, and a diffusion prevention film formed between the organic resin film and the main surface of the semiconductor substrate and between the organic resin film and the side surface and the end portion of the upper surface of the Cu electrode, being in contact therewith.Type: GrantFiled: February 16, 2015Date of Patent: August 1, 2017Assignee: Mitsubishi Electric CorporationInventors: Motoru Yoshida, Kazuyo Endo, Jun Fujita, Hiroaki Okabe, Kazuyuki Sugahara