Abstract: A semiconductor memory device comprises: a semiconductor substrate comprising a first and a second surface; a first and a second electrode provided on a first surface side; a third and a fourth electrode provided on a second surface side; a first through-electrode connected to the first and the third electrode; a second through-electrode connected to the second and the fourth electrode; and a first insulating layer comprising a first and a second portion. The semiconductor substrate comprises: a first impurity region of N type facing a surface of the first through-electrode via the first portion; a second impurity region of N type facing a surface of the second through-electrode via the second portion; and a third impurity region of P type provided between the first and the second impurity region.

Abstract: According to one embodiment, an interconnection substrate includes an insulating layer. A first interconnection layer is on a first side of the insulating layer. A second interconnection layer is on a second side of the insulating layer, which is opposite the first side. A first film comprising carbon covers at least part of the first and second interconnection layers.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first electrode extending in a first direction through the semiconductor substrate between the first surface and the second surface, a first wiring layer on the first surface and electrically connected to the first electrode, and a second wiring layer on the first wiring layer, the first wiring layer being between the semiconductor substrate and the second wiring layer in the first direction. The second wiring layer includes a connection region at which a second electrode is connected and a first air gap between the connection region and an outer edge of the second wiring layer in a second direction crossing the first direction.

Abstract: A semiconductor memory device comprises: a semiconductor substrate comprising a first and a second surface; a first and a second electrode provided on a first surface side; a third and a fourth electrode provided on a second surface side; a first through-electrode connected to the first and the third electrode; a second through-electrode connected to the second and the fourth electrode; and a first insulating layer comprising a first and a second portion. The semiconductor substrate comprises: a first impurity region of N type facing a surface of the first through-electrode via the first portion; a second impurity region of N type facing a surface of the second through-electrode via the second portion; and a third impurity region of P type provided between the first and the second impurity region.

Abstract: A semiconductor device inspection device includes a semiconductor device stage, a sound wave generator, a laser emitter, a photoreceiver, and a processing circuit. The sound wave generator is configured to generate a sound wave having a natural frequency of a bonding wire included in a semiconductor device placed on the semiconductor device stage. The laser emitter is configured to direct laser toward the bonding wire while the sound wave generator generates the sound wave. The photoreceiver is configured to receive the laser reflected by the bonding wire and output a signal corresponding to the received laser. The processing circuit is configured to detect a bonding failure of the bonding wire based on the signal output by the photoreceiver.

Abstract: A semiconductor device inspection device includes a semiconductor device stage, a sound wave generator, a laser emitter, a photoreceiver, and a processing circuit. The sound wave generator is configured to generate a sound wave having a natural frequency of a bonding wire included in a semiconductor device placed on the semiconductor device stage. The laser emitter is configured to direct laser toward the bonding wire while the sound wave generator generates the sound wave. The photoreceiver is configured to receive the laser reflected by the bonding wire and output a signal corresponding to the received laser. The processing circuit is configured to detect a bonding failure of the bonding wire based on the signal output by the photoreceiver.

Abstract: A semiconductor device according to an embodiment includes a substrate, an ?-ray shielding layer, a first semiconductor chip, and a second semiconductor chip. The ?-ray shielding layer is provided on the substrate. The first semiconductor chip is provided on the ?-ray shielding layer. The second semiconductor chip is provided on the first semiconductor chip, whose operation is controlled by the first semiconductor chip.

Abstract: A semiconductor device according to an embodiment includes a substrate, an ?-ray shielding layer, a first semiconductor chip, and a second semiconductor chip. The ?-ray shielding layer is provided on the substrate. The first semiconductor chip is provided on the ?-ray shielding layer. The second semiconductor chip is provided on the first semiconductor chip, whose operation is controlled by the first semiconductor chip.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first electrode extending in a first direction through the semiconductor substrate between the first surface and the second surface, a first wiring layer on the first surface and electrically connected to the first electrode, and a second wiring layer on the first wiring layer, the first wiring layer being between the semiconductor substrate and the second wiring layer in the first direction. The second wiring layer includes a connection region at which a second electrode is connected and a first air gap between the connection region and an outer edge of the second wiring layer in a second direction crossing the first direction.

Abstract: A testing apparatus for a wafer having a plurality of semiconductor chips, each including one or more vias, includes an electron beam discharging unit, a detecting unit, and a controller. The electron beam discharging unit is configured to discharge an electron beam to a via of one of the semiconductor chips. The detecting unit generates a detection signal corresponding to a current flowing through the via. The controller is configured to record a value of the detection signal in association with a position of the semiconductor chip.

Abstract: A fault detection apparatus is provided, including a measurement unit that measures a first time period taken until a reflection signal reflected on a fault of a test apparatus is received after a first signal is transmitted to the test apparatus; a memory unit that includes a CAD data unit having CAD data of the test apparatus and a model data unit to store model data indicating a relation between the first time period and a predicted conduction distance of the first signal; a control unit that calculates a range of a test object selected in the test apparatus, calculates the predicted conduction distance from the first time period based on the model data, and specifies a position of the fault which is separated by the predicted conduction distance from the measurement unit in said range; and a display unit that displays the position of the fault.

Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a first opening that extends from a second surface of a semiconductor substrate opposite to a first surface toward the first surface and extending to a first insulating layer in the semiconductor substrate, performing a first annealing process in a first gas atmosphere that contains hydrogen after formation of the first opening, forming a second insulating layer on a side wall of the semiconductor substrate in the first opening, performing a second annealing process after formation of the second insulating layer, forming a second opening that extends to the conductive layer in the first insulating layer through the first opening, and forming a via that is connected to the conductive layer in the first and second openings.

Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a first opening that extends from a second surface of a semiconductor substrate opposite to a first surface toward the first surface and extending to a first insulating layer in the semiconductor substrate, performing a first annealing process in a first gas atmosphere that contains hydrogen after formation of the first opening, forming a second insulating layer on a side wall of the semiconductor substrate in the first opening, performing a second annealing process after formation of the second insulating layer, forming a second opening that extends to the conductive layer in the first insulating layer through the first opening, and forming a via that is connected to the conductive layer in the first and second openings.

Abstract: A testing apparatus for a wafer having a plurality of semiconductor chips, each including one or more vias, includes an electron beam discharging unit, a detecting unit, and a controller. The electron beam discharging unit is configured to discharge an electron beam to a via of one of the semiconductor chips. The detecting unit generates a detection signal corresponding to a current flowing through the via. The controller is configured to record a value of the detection signal in association with a position of the semiconductor chip.

Abstract: A fault detection apparatus according to an embodiment is provided with a measurement unit, a memory unit, a control unit, and a display unit. The measurement unit measures a first time period taken until a reflection signal reflected on a fault of a test apparatus is received after a first signal is transmitted to the test apparatus. The memory unit includes a CAD data unit having CAD data of the test apparatus, and a model data unit to store model data indicating a relation between the first time period and a predicted conduction distance of the first signal according to the CAD data. The control unit calculates a range of a test object selected in the test apparatus based on the CAD data, calculates the predicted conduction distance from the first time period based on the model data, and specifies a position of a fault of the test apparatus which is separated by the predicted conduction distance from the measurement unit in the range of the test object.

Abstract: A holder for measurement configured to be capable of holding an object of measurement, the object of measurement included a package including a plurality of semiconductor chips and a conduction portion exposed to the outside through a lateral surface of the package, including: a support board including a through-hole; a fixation portion configured to fix the object of measurement to the support board; and a probe portion movable in at least one axial direction with respect to the support board, and configured to be capable of coming into contact with the conduction portion.