Patents by Inventor Motoshige Igarashi

Motoshige Igarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8269284
    Abstract: There are provided a method of manufacturing a semiconductor device which achieves a reduction in implantation masks, and such a semiconductor device. By implanting boron into NMOS regions using a resist mask and another resist mask as the implantation masks, p-type impurity regions serving as the halo regions of access transistors and drive transistors are formed. By further implanting phosphorus or arsenic into a PMOS region using another resist mask as the implantation mask, n-type impurity regions serving as the halo regions of load transistors are formed.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: September 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Nil, Motoshige Igarashi
  • Publication number: 20120187504
    Abstract: A semiconductor device has a high-speed circuit and a high-density circuit, each having at least two field effect transistors and two gate electrodes. In the high-speed circuit, a first gate electrode of a first field effect transistor and a second gate electrode of a second field effect transistor are separated by a first pitch. In the high-density circuit, a third gate electrode of a third field effect transistor and a fourth gate electrode of a fourth field effect transistor are separated by a second pitch. The first pitch is larger than the second pitch. Provision of a notch in the third gate electrode of the third field effect transistor in the high-density circuit, at a portion reached by a shared contact hole shared by the third gate electrode and the fourth transistor, increases the contact area between the shared contact hole and an impurity region source/drain of the fourth transistor.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 26, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Motoshige Igarashi, Yuki Igarashi
  • Patent number: 8183114
    Abstract: A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: May 22, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuo Tsuboi, Motoshige Igarashi
  • Patent number: 8110878
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: February 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Naozumi Morino, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
  • Patent number: 8089136
    Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: January 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Amishiro, Toshio Kumamoto, Motoshige Igarashi, Kenji Yamaguchi
  • Publication number: 20110266631
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Application
    Filed: July 8, 2011
    Publication date: November 3, 2011
    Inventors: Naozumi MORINO, Atsushi HIRAIWA, Kazutoshi OKU, Toshiaki ITO, Motoshige IGARASHI, Takayuki SASAKI, Masao SUGIYAMA, Hiroshi YANAGITA, Shinichi WATARAI
  • Publication number: 20110193173
    Abstract: There are provided a method of manufacturing a semiconductor device which achieves a reduction in implantation masks, and such a semiconductor device. By implanting boron into NMOS regions using a resist mask and another resist mask as the implantation masks, p-type impurity regions serving as the halo regions of access transistors and drive transistors are formed. By further implanting phosphorus or arsenic into a PMOS region using another resist mask as the implantation mask, n-type impurity regions serving as the halo regions of load transistors are formed.
    Type: Application
    Filed: February 2, 2011
    Publication date: August 11, 2011
    Inventors: Koji NII, Motoshige Igarashi
  • Patent number: 7982271
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: July 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Naozumi Morino, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
  • Publication number: 20110024847
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Application
    Filed: October 11, 2010
    Publication date: February 3, 2011
    Inventors: NAOZUMI MORINO, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
  • Publication number: 20110012231
    Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.
    Type: Application
    Filed: September 27, 2010
    Publication date: January 20, 2011
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroyuki AMISHIRO, Toshio Kumamoto, Motoshige Igarashi, Kenji Yamaguchi
  • Patent number: 7821076
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Grant
    Filed: April 12, 2009
    Date of Patent: October 26, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Naozumi Morino, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
  • Patent number: 7821078
    Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: October 26, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Amishiro, Toshio Kumamoto, Motoshige Igarashi, Kenji Yamaguchi
  • Publication number: 20100093145
    Abstract: A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.
    Type: Application
    Filed: December 11, 2009
    Publication date: April 15, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Nobuo TSUBOI, Motoshige Igarashi
  • Patent number: 7663193
    Abstract: A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: February 16, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Nobuo Tsuboi, Motoshige Igarashi
  • Publication number: 20090278204
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Application
    Filed: April 12, 2009
    Publication date: November 12, 2009
    Inventors: Naozumi MORINO, Atsushi HIRAIWA, Kazutoshi OKU, Toshiaki ITO, Motoshige IGARASHI, Takayuki SASAKI, Masao SUGIYAMA, Hiroshi YANAGITA, Shinichi WATARAI
  • Publication number: 20090026520
    Abstract: A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.
    Type: Application
    Filed: September 25, 2008
    Publication date: January 29, 2009
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Nobuo TSUBOI, Motoshige Igarashi
  • Patent number: 7439153
    Abstract: A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: October 21, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Nobuo Tsuboi, Motoshige Igarashi
  • Publication number: 20080116526
    Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.
    Type: Application
    Filed: January 11, 2008
    Publication date: May 22, 2008
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Hiroyuki Amishiro, Toshio Kumamoto, Motoshige Igarashi, Kenji Yamaguchi
  • Publication number: 20080042218
    Abstract: The semiconductor memory device which can suppress that the characteristics variation of a transistor increases in connection with microfabrication is offered. In the memory cell of the present invention, channel width of an access transistor is made larger than the channel width of a driver transistor about the relation of the channel width of an access transistor and a driver transistor. That is, since the access transistor can make channel area increase from the driver transistor designed with the minimum designed size, it becomes possible to suppress the increase in the characteristics variation of an access transistor.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 21, 2008
    Inventors: Motoshige IGARASHI, Nobuo Tsuboi, Toshihumi Iwasaki, Koji Nii, Yasumasa Tsukamoto
  • Publication number: 20070080423
    Abstract: A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.
    Type: Application
    Filed: October 3, 2006
    Publication date: April 12, 2007
    Inventors: Nobuo Tsuboi, Motoshige Igarashi