Abstract: A semiconductor device according to an embodiment includes a level detection unit that validates a level detection signal LD when a value indicated by stream data exceeds a threshold condition value, a ring buffer that cyclically stores internal data generated from the stream data in a storage area that is set within a predetermined address range, a data processing unit that operates with a bus clock and performs data processing using the internal data acquired from the ring buffer, and an address adjustment unit that adjusts a read address indicating a read start position of the ring buffer to a position that becomes a predetermined difference from a write address of the ring buffer at that time in accordance with a start of generation of the bus clock, and generates a bus clock during a period in which the level detection signal LD is valid.

Abstract: A data transfer device that divides and transfers the transfer target data in a burst manner from a transmission-side device to a reception-side device includes a storage device and a control device that controls the storage device to store one piece of the input transfer target data, controls the storage device so that data transfer is performed at a set burst length as a data length of divided data when the one piece of the data is divided by a division number until a last part of the data is sensed, and when the last part of the data is sensed, controls the storage device to adjust the burst length so that a data length of the data coincides with a total of data lengths of data to be transferred, and to transfer the data at the adjusted burst length.

Abstract: A device according to one embodiment includes a first battery to output alternating-current power for driving a motor and connected to a first main circuit that is connected to an inverter; a second battery connected to a second main circuit, having a storage capacity larger than it of the first battery, and having a permissible power output per unit storage capacity smaller than it of the first battery; a DC/DC converter to convert a voltage of the second main circuit to a predetermined voltage and output to the first main circuit; a control circuit to control charging and discharging operations of the first and the second battery and an operation of the DC/DC converter; a first terminal connected to a positive terminal of the first battery; and a second terminal connected to a negative terminal of the first battery.

Abstract: A semiconductor device including an image sensor device controlled by an adjusting circuit, and the adjusting circuit configured to transmit a control signal to the image sensor device to be controlled according to a transmission cycle synchronized with a reference clock, the image sensor device includes a first period during which the control signal is allowed to be supplied to the image sensor device to be controlled and a second period during which the supplying of the control signal to the image sensor device to be controlled is not preferable compared to that in the first period, the adjusting circuit is configured to, when a transmission timing of the control signal determined according to the transmission cycle is within the second period, adjust the transmission timing of the control signal so that the control signal will be transmitted in the first period to the image sensor device.

Abstract: A semiconductor device including an image sensor device controlled by an adjusting circuit, and the adjusting circuit configured to transmit a control signal to the image sensor device to be controlled according to a transmission cycle synchronized with a reference clock, the image sensor device includes a first period during which the control signal is allowed to be supplied to the image sensor device to be controlled and a second period during which the supplying of the control signal to the image sensor device to be controlled is not preferable compared to that in the first period, the adjusting circuit is configured to, when a transmission timing of the control signal determined according to the transmission cycle is within the second period, adjust the transmission timing of the control signal so that the control signal will be transmitted in the first period to the image sensor device.

Abstract: A semiconductor device includes an adjusting circuit that transmits a control signal to a device to be controlled according to a transmission cycle synchronized with a reference clock. The device to be controlled has a first period during which the control signal is allowed to be supplied to the device to be controlled and a second period during which the supplying of the control signal to the device to be controlled is not preferable compared to that in the first period. The adjusting circuit is configured to, when a transmission timing of the control signal determined according to the transmission cycle is within the second period, adjust the transmission timing of the control signal so that the control signal will be transmitted in the first period.

Abstract: A semiconductor device includes an adjusting circuit that transmits a control signal to a device to be controlled according to a transmission cycle synchronized with a reference clock. The device to be controlled has a first period during which the control signal is allowed to be supplied to the device to be controlled and a second period during which the supplying of the control signal to the device to be controlled is not preferable compared to that in the first period. The adjusting circuit is configured to, when a transmission timing of the control signal determined according to the transmission cycle is within the second period, adjust the transmission timing of the control signal so that the control signal will be transmitted in the first period.

Abstract: A receiving apparatus according to the present invention is able to normally decode reception data even when a part of an initialization symbol during training is corrupted. The receiving apparatus includes an initialization signal generation unit that generates an initialization signal, and a descrambling circuit that descrambles reception data by a descrambler initialized by the initialization signal. The reception data includes a training data set for establishing connection of high-speed serial communication, the training data set including one or more TSn ordered sets. The TSn ordered set includes one or more COM symbols and one or more pieces of data other than COM symbols. The initialization signal generation unit generates the initialization signal at an initialization last timing at which at least the last COM symbol among the COM symbols forming the last TSn ordered set included in the training data set is input to the descrambling circuit.

Abstract: A data reception device that receives scrambled and transmission data as received data and that descrambles and outputs the data after adjusting the timing with the transmitter has a descramble circuit 10 detect timing adjustment data included in a timing adjustment data set that adjusts the timing with the transmitter in the data which the descramble circuit 10 has not descrambled, and comprises an LFSR suspending signal generation circuit 9 that outputs a required number of LFSR suspending signals, after first normal timing adjustment data has been received, at the output timing of data received thereafter so as to simulate a situation as if a desired number of timing adjustment data included in the timing adjustment data set were received.

Abstract: A receiving apparatus according to the present invention is able to normally decode reception data even when a part of an initialization symbol during training is corrupted. The receiving apparatus includes an initialization signal generation unit that generates an initialization signal, and a descrambling circuit that descrambles reception data by a descrambler initialized by the initialization signal. The reception data includes a training data set for establishing connection of high-speed serial communication, the training data set including one or more TSn ordered sets. The TSn ordered set includes one or more COM symbols and one or more pieces of data other than COM symbols. The initialization signal generation unit generates the initialization signal at an initialization last timing at which at least the last COM symbol among the COM symbols forming the last TSn ordered set included in the training data set is input to the descrambling circuit.

Abstract: A data reception device that receives scrambled and transmission data as received data and that descrambles and outputs the data after adjusting the timing with the transmitter has a descramble circuit 10 detect timing adjustment data included in a timing adjustment data set that adjusts the timing with the transmitter in the data which the descramble circuit 10 has not descrambled, and comprises an LFSR suspending signal generation circuit 9 that outputs a required number of LFSR suspending signals, after first normal timing adjustment data has been received, at the output timing of data received thereafter so as to simulate a situation as if a desired number of timing adjustment data included in the timing adjustment data set were received.

Abstract: A data receiving device includes an elastic buffer which receives data as receiving data and adjusts timing with a sender, the data being scrambled and sent from the sender, an interpolation circuit which performs predetermined interpolation processing on the data subjected to timing adjustment by the elastic buffer to output the data, and a descramble circuit which descrambles the data output from the interpolation circuit. The receiving data includes data set for adjusting timing. The data set is for adjusting timing with the sender. The interpolation circuit replaces existing data with data for adjusting timing and outputs the data for adjusting timing as required after first receiving normal data for adjusting timing so that a desired number of data for adjusting timing is included in the data set for adjusting timing.