Abstract: A semiconductor wafer is prepared. The wafer has a first and a second surface opposite to each other, and has a recess portion and a rim portion. The semiconductor wafer has semiconductor elements formed on the first surface. The rim portion surrounds the recess portion. The recess portion and the rim portion are composed of the first and second surfaces. The recess portion is formed so as to recede toward the first surface. A tape is adhered to the second surface of the semiconductor wafer. At least the recess portion of the semiconductor wafer is placed on a stage. The tape is sandwiched between the recess portion and the stage. Laser beam is irradiated to the recess portion from the side of the first surface and along predetermined dicing lines. The recess portion is cut off to divide the semiconductor wafer into chips.

Abstract: A method for manufacturing a semiconductor device from a semiconductor wafer having a first major surface, a recess provided inside a periphery on opposite side of the first major surface and surrounded by the periphery, and a second major surface provided at bottom of the recess is provided. The method comprises: fitting into the recess a doping mask having selectively formed openings to selectively cover the second major surface with the doping mask; and selectively introducing dopant into the second major surface.

Abstract: There is provided a method for manufacturing a semiconductor device which is capable of stably forming a plated layer on a plating base layer while adhered chippings are reduced. The method includes forming an insulating film covering at least a base metal on a diffusion region of a semiconductor substrate, forming an organic coating film having an opening at least at a surface section of the base metal being to be exposed on the insulating film, pasting a surface protection tape on the semiconductor substrate to cover the insulating film and the organic coating film, polishing a back surface of the semiconductor substrate that opposes the base metal, removing the surface protection tape, etching the insulating film with the organic coating film used as a mask to expose the base metal and forming a conductive plated layer on the base metal.

Abstract: A wafer with an orientation notch being cut in a portion of its circumference, the wafer includes: a reinforcing flange formed upright at periphery; and a thin section surrounded by the reinforcing flange and having a smaller thickness than the reinforcing flange. The reinforcing flange includes a circumferential portion formed upright along the circumference and a notch portion formed upright near the orientation notch, and a width of the circumferential portion as viewed parallel to a major surface of the wafer is smaller than a depth of the orientation notch as viewed parallel to the major surface.

Abstract: A semiconductor device includes: a semiconductor layer having a first major surface, a second major surface provided on opposite side of the first major surface, and a channel formation region provided in a surface portion on the first major surface side; a first main electrode provided inside a dicing street on the first major surface of the semiconductor layer; a second main electrode provided inside a dicing street on the second major surface of the semiconductor layer; and a control electrode opposed to the channel formation region across an insulating film.

Abstract: A wafer with an orientation notch being cut in a portion of its circumference, the wafer includes: a reinforcing flange formed upright at periphery; and a thin section surrounded by the reinforcing flange and having a smaller thickness than the reinforcing flange. The reinforcing flange includes a circumferential portion formed upright along the circumference and a notch portion formed upright near the orientation notch, and a width of the circumferential portion as viewed parallel to a major surface of the wafer is smaller than a depth of the orientation notch as viewed parallel to the major surface.

Abstract: A semiconductor wafer is prepared. The wafer has a first and a second surface opposite to each other, and has a recess portion and a rim portion. The semiconductor wafer has semiconductor elements formed on the first surface. The rim portion surrounds the recess portion. The recess portion and the rim portion are composed of the first and second surfaces. The recess portion is formed so as to recede toward the first surface. A tape is adhered to the second surface of the semiconductor wafer. At least the recess portion of the semiconductor wafer is placed on a stage. The tape is sandwiched between the recess portion and the stage. Laser beam is irradiated to the recess portion from the side of the first surface and along predetermined dicing lines. The recess portion is cut off to divide the semiconductor wafer into chips.

Abstract: A wafer with an orientation notch being cut in a portion of its circumference, the wafer includes: a reinforcing flange formed upright at periphery; and a thin section surrounded by the reinforcing flange and having a smaller thickness than the reinforcing flange. The reinforcing flange includes a circumferential portion formed upright along the circumference and a notch portion formed upright near the orientation notch, and a width of the circumferential portion as viewed parallel to a major surface of the wafer is smaller than a depth of the orientation notch as viewed parallel to the major surface.

Abstract: A semiconductor device, includes: a semiconductor substrate of 100 micrometers or less in thickness; an electrode pattern formed above the semiconductor substrate; and an insulation film of 50 micrometers or greater in thickness residing on parts of the upper surface side of the semiconductor substrate other than at least on the electrode pattern.

Abstract: A semiconductor device includes: a semiconductor layer having a first major surface, a second major surface provided on opposite side of the first major surface, and a channel formation region provided in a surface portion on the first major surface side; a first main electrode provided inside a dicing street on the first major surface of the semiconductor layer; a second main electrode provided inside a dicing street on the second major surface of the semiconductor layer; and a control electrode opposed to the channel formation region across an insulating film.

Abstract: A method for manufacturing a semiconductor device, includes; measuring a within-wafer distribution of a physical quantity; and etching the wafer so that the physical quantity get close to constant within the wafer. Alternatively, a method for manufacturing a semiconductor device, includes, measuring a within-wafer distribution of a physical quantity of at least one of a plurality of semiconductor layers provided in a wafer; determining a within-wafer distribution of etching amount for the at least one of the plurality of semiconductor layers based on the measured within-wafer distribution of the physical quantity; and etching the at least one of the plurality of semiconductor layers based on the determined within-wafer distribution of the etching amount so that the etching amount is locally varied within the wafer.

Abstract: A method for manufacturing a semiconductor device from a semiconductor wafer having a first major surface, a recess provided inside a periphery on opposite side of the first major surface and surrounded by the periphery, and a second major surface provided at bottom of the recess is provided. The method comprises: fitting into the recess a doping mask having selectively formed openings to selectively cover the second major surface with the doping mask; and selectively introducing dopant into the second major surface.

Abstract: A semiconductor device, comprises: a semiconductor substrate of 100 micrometers or less in thickness; an electrode pattern formed above the semiconductor substrate; and an insulation film of 50 micrometers or greater in thickness residing on parts of the upper surface side of the semiconductor substrate other than at least on the electrode pattern.

Abstract: A semiconductor device comprises a first base layer for providing a PT-IGBT or IEGT structure, which includes a buffer layer and a collector layer provided in the buffer layer. A first activation rate, defined by an activated first conductivity type impurity density [cm−2] in the buffer layer due to SR analysis/a first conductivity type impurity density [cm−2] in the buffer layer due to SIMS analysis is given by 25% or more, and a second activation rate, defined by an activated second conductivity type impurity density [cm−2] in the collector layer due to SR analysis/a second conductivity type impurity density [cm−2] in the collector layer duet to SIMS analysis is given by more than 0% and 10% or less.

Abstract: A laser heating apparatus for forming an electrode on one surface of an Si chip provided on an Si wafer, thereby producing a semiconductor element, comprises a high vacuum chamber having a light transmission window, an XY table contained in the high vacuum chamber for mounting the Si wafer thereon, heater contained in the high vacuum chamber for heating and evaporating an impurity in a solid state, and laser beam applying means for applying a laser beam to the Si chip placed on the XY table from the outside of the high vacuum chamber through the light transmission window, thereby implanting the impurity into the Si in chip and activating the implanted impurity.

Abstract: An N+ buffer layer formed on the underside of an N− layer includes an inactive region having incompletely activated ions and an active region having highly activated ions. The carrier concentration of the active region is higher than that of the inactive region. In the inactive region, the electrical activation rate X of the ions is expressed as 1%≦X≦30%. It is thus possible to achieve a PT structure using a Raw wafer, which reduces manufacturing costs and suppresses power consumption.

Abstract: A semiconductor device comprises a first base layer for providing a PT-IGBT or IEGT structure, which includes a buffer layer and a collector layer provided in the buffer layer. A first activation rate, defined by an activated first conductivity type impurity density [cm−2] in the buffer layer due to SR analysis/a first conductivity type impurity density [cm−2] in the buffer layer due to SIMS analysis is given by 25% or more, and a second activation rate, defined by an activated second conductivity type impurity density [cm−2] in the collector layer due to SR analysis/a second conductivity type impurity density [cm−2] in the collector layer duet to SIMS analysis is given by more than 0% and 10% or less.

Abstract: An insulated gate bipolar transistor is disclosed, which comprises a first conductivity type base layer, a second conductivity type base layer and an emitter layer which are selectively formed in an upper surface of the first conductivity type base layer, a buffer layer and a collector layer which are formed on a back surface of the first conductivity type base layer. A requirement of d2/d1>1.5 is satisfied, where d1 is a depth in the buffer layer, as measured from an interface of the buffer layer and the collector layer, at which a first conductivity type impurity concentration in the buffer layer shows a peak value, and d2 is a shallowest depth in the buffer layer, as measured from the interface of the buffer layer and the collector layer, at which an activation ratio of the first conductivity type impurity in the buffer layer is a predetermined value.