Abstract: A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench formed in the first interlayer insulation film and having a sidewall surface and a bottom surface covered with a first barrier metal film, a via-hole formed in the second interlayer insulation film and having a sidewall surface and a bottom surface covered with a second barrier metal film, an interconnection pattern filling the interconnection trench, and a via-plug filling the via-hole, wherein the via-plug makes a contact with a surface of the interconnection pattern, the interconnection pattern has projections and depressions on the surface, the interconnection pattern containing therein oxygen atoms along a crystal grain boundary extending from the surface toward an interior of the interconnection pattern with a concentration higher than a concentration at the surface.

Abstract: A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench formed in the first interlayer insulation film and having a sidewall surface and a bottom surface covered with a first barrier metal film, a via-hole formed in the second interlayer insulation film and having a sidewall surface and a bottom surface covered with a second barrier metal film, an interconnection pattern filling the interconnection trench, and a via-plug filling the via-hole, wherein the via-plug makes a contact with a surface of the interconnection pattern, the interconnection pattern has projections and depressions on the surface, the interconnection pattern containing therein oxygen atoms along a crystal grain boundary extending from the surface toward an interior of the interconnection pattern with a concentration higher than a concentration at the surface.

Abstract: A method is provided for manufacturing a semiconductor device having a multilayer wiring structure in which at least one insulating film is formed with a set of conducting portions which are electrically connected to each other to have a surface area of no less than 500 ?m2 and which include a wiring having a width of no more than 1.0 ?m. The method includes a polishing step for flattening the conducting portions together with the insulating film by chemical mechanical polishing, a chemical cleaning step for cleaning the flattened surface of the insulating film with a cleaning liquid, and a rising step for removing the cleaning liquid using a rinsing liquid. The rinsing step is performed using water with a dissolved oxygen concentration decreased to no more than 6 ppm by weight as the rinsing liquid.

Abstract: A method of manufacturing a semiconductor device, comprising the steps of washing the surface of a substrate having insulation areas and metal areas exposed to the surface by using organic cleaning solvent, and radiating ultra-violet ray on the surface of the washed substrate, whereby the accumulation of a residue on the surface of the substrate can be suppressed.

Abstract: There is provided a chamber open to the outside through openings through which a solder-adhered object is passed and the chamber having a heating/melting area, a carrying mechanism for carrying the solder-adhered object into the heating/melting area, a formic-acid supplying means for supplying a formic acid into the heating/melting area, an exhausting means for exhausting a gas from the heating/melting area and its neighboring area to create a lower pressure area in the heating/melting area as compared to the pressure of outside the chamber, heating means for heating directly or indirectly the solder-adhered object in the heating/melting area, and an air-stream suppressing means for disturbing a gas flow between the heating/melting area and the carrying areas.

Abstract: A first insulating film is formed on an underlying substrate, the first insulating film being made of a first insulating material. A second insulating film is formed on the first insulating film, the second insulating film being made of a second insulating material different from the first insulating material. A trench is formed through the second and first insulating film, the trench reaching at least an intermediate depth of the first insulating film. A wiring layer made of a conductive material is deposited on the second insulating film, the wiring layer burying the trench. The wiring layer is polished to leave the wiring layer in the trench. The wiring layer and second insulating film are polished until the first insulating film is exposed. Irregularity such as dishing and erosion can be suppressed from being formed.

Abstract: A first insulating film is formed on an underlying substrate, the first insulating film being made of a first insulating material. A second insulating film is formed on the first insulating film, the second insulating film being made of a second insulating material different from the first insulating material. A trench is formed through the second and first insulating film, the trench reaching at least an intermediate depth of the first insulating film. A wiring layer made of a conductive material is deposited on the second insulating film, the wiring layer burying the trench. The wiring layer is polished to leave the wiring layer in the trench. The wiring layer and second insulating film are polished until the first insulating film is exposed. Irregularity such as dishing and erosion can be suppressed from being formed.

Abstract: A method is provided for manufacturing a semiconductor device having a multilayer wiring structure in which at least one insulating film is formed with a set of conducting portions which are electrically connected to each other to have a surface area of no less than 500 &mgr;m2 and which include a wiring having a width of no more than l.0 &mgr;m. The method includes a polishing step (501) for flattening the conducting portions together with the insulating film by chemical mechanical polishing, a chemical cleaning step (502) for cleaning the flattened surface of the insulating film with a cleaning liquid, and a rising step (503) for removing the cleaning liquid using a rinsing liquid. The rinsing step is performed using water with a dissolved oxygen concentration decreased to no more than 6 ppm by weight as the rinsing liquid.

Abstract: There are provided a chamber having openings which are opened to an outer air and through which a solder-adhered object w is passed and having a heating/melting area and carrying areas arranged adjacent to the heating/melting area, a carrying mechanism for carrying the solder-adhered object w into the heating/melting area, a formic-acid supplying means for supplying a formic acid into the heating/melting area, an exhausting means for exhausting a gas from the heating/melting area and its neighboring area to lower a pressure in the heating/melting area rather than an outer air, heating means for heating directly or indirectly the solder-adhered object w in the heating/melting area, and air-stream suppressing means for disturbing a gas flow between the heating/melting area and the carrying areas.

Abstract: The present invention relates to a semiconductor device manufacturing method containing the step of polishing an insulating oxide film having an uneven surface, to improve a throughput in burying the insulating film into trenches and also improve flatness of a polished surface.

Abstract: The present invention relates to a semiconductor device manufacturing method containing the step of polishing an insulating oxide film having an uneven surface, to improve a throughput in burying the insulating film into trenches and also improve flatness of a polished surface.

Abstract: This invention discloses a polishing method for flattening an inter-level insulating film or polycrystalline silicon inside a device isolation ditch in a semiconductor fabrication process.To this end, the present invention grinds and flattens an insulating film having a step on the surface thereof by using a polishing solution containing an alkali solution and a grain, wherein a cation concentration in the alkali solution is higher than an OH.sup.- ion concentration in the alkali solution.

Abstract: A bipolar transistor having self-aligned base and emitter regions is fabricated in a silicon layer which is epitaxially grown on a substrate so as to fill up a cavity formed through a polysilicon layer deposited on the substrate. The polysilicon layer is doped with impurities for creating an extrinsic base region in the epitaxially grown silicon layer and is insulated from the emitter electrode by a dielectric layer formed thereon. The dielectric layer can be provided by selectively oxidizing the polysilicon layer. Thus, the step formed at the emitter electrode is small and equal to the thickness of the dielectric layer, about 3000 .ANG., for example, thereby eliminating the faulty step coverage in the prior art self-aligned bipolar transistor usually having the step as large as 1 micron.

Abstract: A method of producing a complementary semiconductor device having p-type islands and n-type islands in a dielectric isolation structure, including removing a projecting portion of a polycrystalline silicon layer, which is formed at the same time as the formation of an epitaxial silicon layer for one of two types of islands, so as to obtain an almost smooth exposed surface. The smooth surface contributes to the formation of a good masking pattern on the epitaxial silicon layer by a photoetching method, so that mesa portions for islands having exact dimensions are formed at predetermined positions.