Patents by Inventor Mototsugu Hamada
Mototsugu Hamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8587384Abstract: A semiconductor integrated circuit device includes a DCO and a storing unit that stores a temperature coefficient of an oscillation frequency and an absolute value of the oscillation frequency, which should be set in the DCO, corresponding to potential obtained from a voltage source that changes with a monotonic characteristic with respect to temperature.Type: GrantFiled: November 10, 2011Date of Patent: November 19, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yuji Satoh, Mototsugu Hamada, Daisuke Miyashita
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Patent number: 8134404Abstract: A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.Type: GrantFiled: January 22, 2010Date of Patent: March 13, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuyuki Ashida, Mototsugu Hamada
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Publication number: 20120056682Abstract: A semiconductor integrated circuit device includes a DCO and a storing unit that stores a temperature coefficient of an oscillation frequency and an absolute value of the oscillation frequency, which should be set in the DCO, corresponding to potential obtained from a voltage source that changes with a monotonic characteristic with respect to temperature.Type: ApplicationFiled: November 10, 2011Publication date: March 8, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuji SATOH, Mototsugu HAMADA, Daisuke MIYASHITA
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Patent number: 8067962Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.Type: GrantFiled: September 4, 2009Date of Patent: November 29, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Mototsugu Hamada, Tsuyoshi Nishikawa, Toshiyuki Furusawa
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Publication number: 20110181367Abstract: A semiconductor integrated circuit device includes a DCO and a storing unit that stores a temperature coefficient of an oscillation frequency and an absolute value of the oscillation frequency, which should be set in the DCO, corresponding to potential obtained from a voltage source that changes with a monotonic characteristic with respect to temperature.Type: ApplicationFiled: March 17, 2010Publication date: July 28, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuji SATOH, Mototsugu HAMADA, Daisuke MIYASHITA
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Patent number: 7808017Abstract: A semiconductor integrated circuit having a first p-type MOS transistor; a first n-type MOS transistor; a second p-type MOS transistors; a and second n-type MOS transistors having fourth gate electrodes disposed so as to be adjacent to the second diffused regions of the first n-type MOS transistor. The semiconductor integrated circuit further having an absolute value of a threshold voltage of the second p-type MOS transistor being higher than an absolute value of a threshold voltage of the first p-type MOS transistor, and an absolute value of a threshold voltage of the second n-type MOS transistor being higher than an absolute value of a threshold voltage of the first n-type MOS transistor.Type: GrantFiled: February 1, 2010Date of Patent: October 5, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Mototsugu Hamada
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Patent number: 7733145Abstract: A nonvolatile latch circuit includes: a first gate part controlling to load or intercept an input signal based on a gate signal; a first logic gate functioning as an inverter or a gate outputting a constant voltage in response to the first control signal; a second logic gate functioning as an inverter or a gate outputting the constant voltage in response to the first control signal; a second gate part controlling to load or intercept the output of the second logic gate based on an inverted signal of the gate signal and sends the output of the second logic gate to an first input terminal of the first logic gate; and first and second injection type MTJ elements provided between the driving power supply and the first and second logic gates and changing in resistance depending upon a current flow direction.Type: GrantFiled: August 31, 2007Date of Patent: June 8, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Keiko Abe, Takahiro Hirai, Shiho Nakamura, Hirofumi Morise, Mototsugu Hamada
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Publication number: 20100133625Abstract: A semiconductor integrated circuit having a first p-type MOS transistor; a first n-type MOS transistor; a second p-type MOS transistors; a and second n-type MOS transistors having fourth gate electrodes disposed so as to be adjacent to the second diffused regions of the first n-type MOS transistor. The semiconductor integrated circuit further having an absolute value of a threshold voltage of the second p-type MOS transistor being higher than an absolute value of a threshold voltage of the first p-type MOS transistor, and an absolute value of a threshold voltage of the second n-type MOS transistor being higher than an absolute value of a threshold voltage of the first n-type MOS transistor.Type: ApplicationFiled: February 1, 2010Publication date: June 3, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Mototsugu HAMADA
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Publication number: 20100117161Abstract: A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.Type: ApplicationFiled: January 22, 2010Publication date: May 13, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuyuki ASHIDA, Mototsugu Hamada
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Publication number: 20100066419Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.Type: ApplicationFiled: September 4, 2009Publication date: March 18, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mototsugu Hamada, Tsuyoshi Nishikawa, Toshiyuki Furusawa
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Patent number: 7679106Abstract: A semiconductor integrated circuit having a substantially rectangular standard cell divided by first borderlines opposed to other standard cells longitudinally adjacent to the standard cell and second borderlines opposed to other standard cells laterally adjacent to the standard cell, the standard cell has: a p-type MOS transistor having first diffused regions and a first gate electrode; an n-type MOS transistor having second diffused regions and a second gate electrode with STI disposed for device isolation between the n-type MOS transistor and the p-type MOS transistor substantially in parallel with the first borderlines; dummy p-type MOS transistors having third gate electrodes disposed on the second borderlines so as to be adjacent to the first diffused regions of the p-type MOS transistor, the third gate electrodes being connected to power supply wiring so as to turn off the dummy p-type MOS transistors; and dummy n-type MOS transistors having fourth gate electrodes disposed on the second borderlines soType: GrantFiled: May 5, 2008Date of Patent: March 16, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Mototsugu Hamada
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Patent number: 7675355Abstract: A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.Type: GrantFiled: June 5, 2007Date of Patent: March 9, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuyuki Ashida, Mototsugu Hamada
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Patent number: 7606096Abstract: A semiconductor integrated circuit device, has a first variable resistor element and a second variable resistor element whose resistances are changed complementarily depending on a current; and a current path switching circuit that supplies said current from a power supply by switching between current paths according to whether a normal operation mode or a read mode is input externally, wherein said power supply is turned off and then turned on again in said normal operation mode, and in this state, data corresponding to the relationship between the magnitudes of the resistances of said first variable resistor element and said second variable resistor element is read in said read mode.Type: GrantFiled: October 15, 2007Date of Patent: October 20, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Mototsugu Hamada, TakahirO Hirai, Shiho Nakamura, Hirofumi Morise, Keiko Abe
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Patent number: 7602211Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.Type: GrantFiled: June 3, 2008Date of Patent: October 13, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Mototsugu Hamada, Tsuyoshi Nishikawa, Toshiyuki Furusawa
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Patent number: 7586364Abstract: A power supply voltage controlling circuit has a voltage regulator circuit that supplies a current to an output terminal from at least any of a first power supply and a second power supply, and compares an output voltage at the output terminal with a first reference voltage to adjust the output voltage to approach the first reference voltage; and a controller circuit that supplies the first reference voltage to the voltage regulator circuit and controls the voltage regulator circuit by outputting, to the voltage regulator circuit, at least any of a first enable signal for enabling the first power supply to supply a current to the output terminal and a second enable signal for enabling the second power supply to supply a current to the output terminal.Type: GrantFiled: June 5, 2007Date of Patent: September 8, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Fujita, Mototsugu Hamada
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Patent number: 7551019Abstract: This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.Type: GrantFiled: June 18, 2007Date of Patent: June 23, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Fujita, Mototsugu Hamada, Hiroyuki Hara
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Patent number: 7479806Abstract: The semiconductor integrated circuit device is a semiconductor integrated circuit device having a pulse generator and a latch circuit. The pulse generator has a first charge/discharge path and a second charge/discharge path and a charge unit for pre-charging first nodes. The first charge/discharge path and the second charge/discharge path include: two first switching units, connected to the first nodes, and configured to control, according to an input signal, conduction and non-conduction of the first charge/discharge path and the second charge/discharge path; and a second switching unit, disposed between a second node and a reference voltage node, and configured to be turned on in a period prior to capturing the input signal to allow an electric charge accumulated at the second node to be discharged to the reference voltage node, and at the same time, configured to be turned on in a period of capturing the input signal to allow the first node to discharge.Type: GrantFiled: June 28, 2006Date of Patent: January 20, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Chen Kong Teh, Mototsugu Hamada
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Publication number: 20080298117Abstract: A semiconductor integrated circuit device, has a first variable resistor element and a second variable resistor element whose resistances are changed complementarily depending on a current; and a current path switching circuit that supplies said current from a power supply by switching between current paths according to whether a normal operation mode or a read mode is input externally, wherein said power supply is turned off and then turned on again in said normal operation mode, and in this state, data corresponding to the relationship between the magnitudes of the resistances of said first variable resistor element and said second variable resistor element is read in said read mode.Type: ApplicationFiled: October 15, 2007Publication date: December 4, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mototsugu Hamada, Takahiro Hirai, Shiho Nakamura, Hirofumi Morise, Keiko Abe
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Patent number: 7456669Abstract: A semiconductor integrated circuit device includes a comparator for making a comparison between a logical value of an input signal and a logical value of an output signal and outputting a combination signal having a combination of the logical values; and a flip-flop circuit configured to maintain a state of the output signal with electric power for maintaining the state less than electric power for state transition of the output signal in the case where the combination of the logical values of the combination signal is a predetermined combination, and wherein the comparator outputs the combination signal having the predetermined combination to an input terminal portion in the case of determining that the input signal does not vary the state of the output signal based on a result of the comparison between the logical value of the input signal and the logical value of the output signal.Type: GrantFiled: May 24, 2006Date of Patent: November 25, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Chen Kong Teh, Mototsugu Hamada
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Publication number: 20080283871Abstract: A semiconductor integrated circuit having a substantially rectangular standard cell divided by first borderlines opposed to other standard cells longitudinally adjacent to the standard cell and second borderlines opposed to other standard cells laterally adjacent to the standard cell, the standard cell has: a p-type MOS transistor having first diffused regions and a first gate electrode; an n-type MOS transistor having second diffused regions and a second gate electrode with STI disposed for device isolation between the n-type MOS transistor and the p-type MOS transistor substantially in parallel with the first borderlines; dummy p-type MOS transistors having third gate electrodes disposed on the second borderlines so as to be adjacent to the first diffused regions of the p-type MOS transistor, the third gate electrodes being connected to power supply wiring so as to turn off the dummy p-type MOS transistors; and dummy n-type MOS transistors having fourth gate electrodes disposed on the second borderlines soType: ApplicationFiled: May 5, 2008Publication date: November 20, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Mototsugu HAMADA