Abstract: A clocking converter for asynchronous data capable of performing bit synchronization processes of asynchronous data of different patterns by the same circuit, requiring virtually no change made therein, and shortening the processing time while achieving downscaling of the circuit structure.

Abstract: The present invention relates to an interface conversion circuit for conversion of the frame structure of a first interface, such as a U-interface, into a second interface to ensure that the phase relation between frame clocks of both the first interface and the second interface is kept constant during communications by absorbing the jitter between the frame clocks of both interfaces when no certain phase relation is established between the frame clocks when the frame structure of the first interface is converted into the second interface. The interface conversion circuit according to the present invention includes a reception timing signal generator and second interface timing signal generator. The reception timing signal generator is adapted to shift the window signal WND and half window signal HWND, respectively, a predetermined number of bits ahead when the second interface frame clock MTC from the second interface timing signal generator lies in the former half of the window signal WND.