Abstract: A working fluid filled in a refrigerant circulation system comprising a compressor, a condenser, an expansion mechanism, an evaporator, and an accumulator, the working fluid comprising: a refrigerant; and a refrigerating machine oil, wherein the refrigerant comprises a hydrocarbon refrigerant having 2 to 4 carbon atoms, the refrigerating machine oil has a mixed aniline point of 20° C. or higher and 50° C. or lower and a viscosity index of 110 or more, an amount of the refrigerant dissolved in the working fluid is 40% by mass or less under conditions of a temperature of 80° C. and an absolute pressure of 2.8 MPa, and the refrigerating machine oil has a kinematic viscosity at ?10° C. of 200 mm2/s or more and 3000 mm2/s or less.

Abstract: An apparatus of a wafer processing apparatus includes at least one memory and logic, at least a portion of which is implemented in circuitry of the wafer processing apparatus including at least one processor coupled to the at least one memory. The logic may provide a 3D model of a surface of a wafer, the wafer defining a wafer plane; and modify a surface feature in a Z-direction along the surface of the wafer based on at least one of: an X-critical dimension (CD) extending along an X-direction of the wafer plane, and a Y-CD extending along a Y direction of the wafer plane.

Abstract: An apparatus of a wafer processing apparatus includes at least one memory and logic, at least a portion of which is implemented in circuitry of the wafer processing apparatus including at least one processor coupled to the at least one memory. The logic may provide a 3D model of a surface of a wafer, the wafer defining a wafer plane; and modify a surface feature in a Z-direction along the surface of the wafer based on at least one of: an X-critical dimension (CD) extending along an X-direction of the wafer plane, and a Y-CD extending along a Y direction of the wafer plane.

Abstract: A first hydroisomerization catalyst contains a support being a extruded product prepared by calcination having a thermal treatment that includes thermally treating at 350° C. or more and at least one metal supported on the support and selected from the group consisting of metals belonging to Groups 8 to 10 of the periodic table, molybdenum and tungsten, wherein the support contains (a1) a calcined zeolite prepared by calcination having a thermal treatment that includes thermally treating at 350° C. or more of an ion-exchanged zeolite obtained by ion exchange of an organic template-containing zeolite containing an organic template and having a 10-membered ring one-dimensional porous structure in a solution containing ammonium ions and/or protons, and (b1) a calcined inorganic oxide prepared by calcination having a thermal treatment that includes thermally treating at 350° C.

Abstract: A first hydroisomerization catalyst contains a support being a extruded product prepared by calcination having a thermal treatment that includes thermally treating at 350° C. or more and at least one metal supported on the support and selected from the group consisting of metals belonging to Groups 8 to 10 of the periodic table, molybdenum and tungsten, wherein the support contains (a1) a calcined zeolite prepared by calcination having a thermal treatment that includes thermally treating at 350° C. or more of an ion-exchanged zeolite obtained by ion exchange of an organic template-containing zeolite containing an organic template and having a 10-membered ring one-dimensional porous structure in a solution containing ammonium ions and/or protons, and (b1) a calcined inorganic oxide prepared by calcination having a thermal treatment that includes thermally treating at 350° C.

Abstract: A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.

Abstract: A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.

Abstract: A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.

Abstract: According to an aspect of the present invention, there is provided a simulation circuit pattern evaluation method including: designing an aggregate of simulation circuit patterns, which simulate a circuit pattern of a semiconductor integrated circuit, by combining plural geometrical structure defining parameters respectively having at least two states in such a manner that the respective states appear the same number of times in the respective geometrical structure defining parameters; forming the aggregate of the simulation circuit patterns on a substrate; and evaluating the formed aggregate of the simulation circuit patterns.

Abstract: A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.

Abstract: According to an aspect of the present invention, there is provided a simulation circuit pattern evaluation method including: designing an aggregate of simulation circuit patterns, which simulate a circuit pattern of a semiconductor integrated circuit, by combining plural geometrical structure defining parameters respectively having at least two states in such a manner that the respective states appear the same number of times in the respective geometrical structure defining parameters; forming the aggregate of the simulation circuit patterns on a substrate; and evaluating the formed aggregate of the simulation circuit patterns.

Abstract: A process for forming a dual-damascene interconnect employs a spun-on organic layer above an interlayer dielectric having a set of apertures for vias that forms tapered regions about the apertures without penetrating the apertures; the slope of the tapered regions being transferred in the etching process to form self-aligned tapered vias.

Abstract: A permanently alterable, i.e., customizable, integrated circuit has a fuse element and contact pad, and windows extending above the same through an insulative layer. The contact pad window extends down to and exposes the contact pad. The fuse element window terminates just short of the fuse element so that the fuse element remains covered by a thin layer of insulative material. The fuse element and the contact pad reside in a common plane of the substrate and thus can be formed together using a single photolithographic transfer step. Windows of different depth are created above the fuse element and contact pad in a single etching step by providing at least one narrow width etching pattern resist aperture above the fuse element. This slows the etch rate at the fused element relative to that at the contact pad, due to a microloading effect.

Abstract: A permanently alterable, i.e., customizable, integrated circuit has a fuse element and contact pad, and windows extending above the same through an insulative layer. The contact pad window extends down to and exposes the contact pad. The fuse element window terminates just short of the fuse element so that the fuse element remains covered by a thin layer of insulative material. The fuse element and the contact pad reside in a common plane of the substrate and thus can be formed together using a single photolithographic transfer step. Windows of different depth are created above the fuse element and contact pad in a single etching step by providing at least one narrow width etching pattern resist aperture above the fuse element. This slows the etch rate at the fused element relative to that at the contact pad, due to a microloading effect.