Abstract: Each ferroelectric memory cell has a ferroelectric capacitor connected between a transfer gate and a plate line, and a coupling capacitor connected between one plate electrode of the ferroelectric capacitor and a common line. For each row in a memory cell array, there are provided an erase switch connected between the common line and an erase potential VE, and another erase switch connected between the plate line and a ground potential, wherein these erase switches are turned on to erase all the memory cells in a lump with activating an erase signal. If an intermediate plate electrode is provided between a pair of the plate electrodes of the ferroelectric capacitor, and connected to the common line, the coupling capacitor can be omitted.