Patents by Inventor Motoyasu Nakao
Motoyasu Nakao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11833543Abstract: An ultrasonic apparatus includes a transmitting circuit, an ultrasonic transducer, a receiving circuit, and a capacitance measuring circuit. The ultrasonic transducer is a three-terminal ultrasonic transducer that includes a transmitting electrode, a receiving electrode, and a common electrode. The transmitting circuit outputs a driving signal to the transmitting electrode to cause the ultrasonic transducer to transmit ultrasonic waves. The receiving circuit receives a receive signal from the receiving electrode. The capacitance measuring circuit is electrically connected to the receiving electrode to measure the electrostatic capacitance of the ultrasonic transducer.Type: GrantFiled: July 16, 2019Date of Patent: December 5, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Motoyasu Nakao, Kosuke Watanabe
-
Patent number: 11772129Abstract: An ultrasonic apparatus includes an ultrasonic transducer, a transmitting circuit, a receiving circuit, a Q-factor measuring circuit, and a frequency measuring circuit. The ultrasonic transducer is a three-terminal ultrasonic transducer that includes a transmitting electrode, a receiving electrode, and a common electrode. The transmitting circuit outputs a driving signal to the transmitting electrode to cause the ultrasonic transducer to transmit ultrasonic waves. The receiving circuit receives a receive signal from the receiving electrode. The frequency measuring circuit measures a resonant frequency of the ultrasonic transducer from a reverberation signal in the receive signal. The Q-factor measuring circuit measures a Q factor of the ultrasonic transducer from the reverberation signal in the receive signal.Type: GrantFiled: July 16, 2019Date of Patent: October 3, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Motoyasu Nakao, Kosuke Watanabe
-
Publication number: 20220192539Abstract: A stiff shoulder evaluation device includes a simultaneous contraction index detection unit and a stiff shoulder evaluation unit. The simultaneous contraction index detection unit detects simultaneous contraction indexes of skeletal muscles at a plurality of positions and in antagonistic relationship with each other. The stiff shoulder evaluation unit evaluates a state of stiff shoulder from the simultaneous contraction index.Type: ApplicationFiled: March 9, 2022Publication date: June 23, 2022Inventors: Takaei KIHARA, Motoyasu NAKAO, Ko MATSUDAIRA, Junji KATSUHIRA
-
Publication number: 20190337015Abstract: An ultrasonic apparatus includes an ultrasonic transducer, a transmitting circuit, a receiving circuit, a Q-factor measuring circuit, and a frequency measuring circuit. The ultrasonic transducer is a three-terminal ultrasonic transducer that includes a transmitting electrode, a receiving electrode, and a common electrode. The transmitting circuit outputs a driving signal to the transmitting electrode to cause the ultrasonic transducer to transmit ultrasonic waves. The receiving circuit receives a receive signal from the receiving electrode. The frequency measuring circuit measures a resonant frequency of the ultrasonic transducer from a reverberation signal in the receive signal. The Q-factor measuring circuit measures a Q factor of the ultrasonic transducer from the reverberation signal in the receive signal.Type: ApplicationFiled: July 16, 2019Publication date: November 7, 2019Inventors: Motoyasu NAKAO, Kosuke WATANABE
-
Publication number: 20190337016Abstract: An ultrasonic apparatus includes a transmitting circuit, an ultrasonic transducer, a receiving circuit, and a capacitance measuring circuit. The ultrasonic transducer is a three-terminal ultrasonic transducer that includes a transmitting electrode, a receiving electrode, and a common electrode. The transmitting circuit outputs a driving signal to the transmitting electrode to cause the ultrasonic transducer to transmit ultrasonic waves. The receiving circuit receives a receive signal from the receiving electrode. The capacitance measuring circuit is electrically connected to the receiving electrode to measure the electrostatic capacitance of the ultrasonic transducer.Type: ApplicationFiled: July 16, 2019Publication date: November 7, 2019Inventors: Motoyasu NAKAO, Kosuke WATANABE
-
Publication number: 20190339370Abstract: An ultrasonic apparatus includes an ultrasonic transducer, a driving circuit, a receiving circuit, a frequency detector, a frequency storage, a temperature detector, and an anomaly determiner. The frequency detector detects a resonant frequency of the ultrasonic transducer. The frequency storage stores a resonant frequency of the ultrasonic transducer at a predetermined temperature. The anomaly determiner determines an anomaly of the ultrasonic transducer based on a temperature detected by the temperature detector, a resonant frequency stored in the frequency storage, and a resonant frequency detected by the frequency detector.Type: ApplicationFiled: July 16, 2019Publication date: November 7, 2019Inventors: Kosuke WATANABE, Motoyasu NAKAO
-
Patent number: 9866195Abstract: A stray capacitance is generated between an antenna element and a ground electrode. A capacitance detection circuit detects the stray capacitance. An antenna matching circuit, is provided along a wireless communication signal path, which is a transmission path between the antenna element and a feeder circuit. A feedback control circuit transmits a control signal to the variable matching circuit on the basis of a detection result of the capacitance detection circuit in accordance with the stray capacitance. The capacitance detection circuit includes a constant current source and a timing circuit to measure the time taken to charge the antenna from the constant current source and for the voltage to reach a predetermined voltage.Type: GrantFiled: July 11, 2017Date of Patent: January 9, 2018Assignee: Murata Manufacturing Co., Ltd.Inventors: Shoji Nagumo, Masashi Nakazato, Motoyasu Nakao, Yuji Shintomi
-
Publication number: 20170310298Abstract: A stray capacitance is generated between an antenna element and a ground electrode. A capacitance detection circuit detects the stray capacitance. An antenna matching circuit, is provided along a wireless communication signal path, which is a transmission path between the antenna element and a feeder circuit. A feedback control circuit transmits a control signal to the variable matching circuit on the basis of a detection result of the capacitance detection circuit in accordance with the stray capacitance. The capacitance detection circuit includes a constant current source and a timing circuit to measure the time taken to charge the antenna from the constant current source and for the voltage to reach a predetermined voltage.Type: ApplicationFiled: July 11, 2017Publication date: October 26, 2017Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Shoji NAGUMO, Masashi NAKAZATO, Motoyasu NAKAO, Yuji SHINTOMI
-
Patent number: 9748917Abstract: A stray capacitance is generated between an antenna element and a ground electrode. A capacitance detection circuit detects the stray capacitance. An antenna matching circuit, is provided along a wireless communication signal path, which is a transmission path between the antenna element and a feeder circuit. A feedback control circuit transmits a control signal to the variable matching circuit on the basis of a detection result of the capacitance detection circuit in accordance with the stray capacitance. The capacitance detection circuit includes a constant current source and a timing circuit to measure the time taken to charge the antenna from the constant current source and for the voltage to reach a predetermined voltage.Type: GrantFiled: July 15, 2014Date of Patent: August 29, 2017Assignee: Murata Manufacturing Co., Ltd.Inventors: Shoji Nagumo, Masashi Nakazato, Motoyasu Nakao, Yuji Shintomi
-
Publication number: 20150311881Abstract: A stray capacitance is generated between an antenna element and a ground electrode. A capacitance detection circuit detects the stray capacitance. An antenna matching circuit, is provided along a wireless communication signal path, which is a transmission path between the antenna element and a feeder circuit. A feedback control circuit transmits a control signal to the variable matching circuit on the basis of a detection result of the capacitance detection circuit in accordance with the stray capacitance. The capacitance detection circuit includes a constant current source and a timing circuit to measure the time taken to charge the antenna from the constant current source and for the voltage to reach a predetermined voltage.Type: ApplicationFiled: July 15, 2014Publication date: October 29, 2015Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Shoji NAGUMO, Masashi NAKAZATO, Motoyasu NAKAO, Yuji SHINTOMI
-
Patent number: 6720850Abstract: A resonance type SPST switch is formed by connecting an inductive element in series with the drain of an FET, and then by connecting a capacitive element in parallel with the series connection of the FET and the inductive element. A constant-voltage source for feeding a voltage Vs is connected to the source of the FET, and a variable-voltage generator for switching the FET between an on state and a state in the vicinity of pinchoff is connected to the gate of the FET. When the variable-voltage generator feeds a voltage V&agr; in the vicinity of a pinchoff voltage to the gate of the FET, the SPST switch is closed while the amount of attenuation between first and second terminals is variably set. The resulting variable attenuator is thus compact in size, allows a large amount of attenuation to be set, and involves low manufacturing costs.Type: GrantFiled: April 2, 2002Date of Patent: April 13, 2004Assignee: Murata Manufacturing Co., Ltd.Inventors: Akihiro Sasabata, Motoyasu Nakao
-
Patent number: 6710426Abstract: A field effect transistor (FET) is formed on a semiconductor substrate. A drain terminal, a source terminal, and a gate terminal connected to the FET are also formed on the semiconductor substrate. In an embodiment of the invention, a metal insulator metal (MIM) capacitor for blocking a bias current is disposed between the FET and the drain terminal. A bias terminal is provided between the MIM capacitor and the FET. Passive circuits connected to the drain terminal, the source terminal, and the gate terminal, and a bias circuit connected to the bias terminal are formed on a dielectric substrate. With this arrangement, the circuitry on the semiconductor substrate can be simplified. The general versatility of a resulting semiconductor device can be increased, and the size of the semiconductor device can be reduced.Type: GrantFiled: March 12, 2003Date of Patent: March 23, 2004Assignee: Murata Manufacturing Co., Ltd.Inventors: Motoyasu Nakao, Akihiro Sasabata
-
Patent number: 6693498Abstract: An SPDT switch used for a communication unit includes first and second terminals, a common terminal, and first and second FETs with Schottky connection gates. The drain of the first FET is connected to the first terminal, and the source of the second FET is connected to the second terminal. The source of the first FET and the drain of the second FET are directly connected to each other, and are then connected to the common terminal. The pinch-off voltage Vp1 of the first FET is set to satisfy 0 >Vp1>&agr;−&ggr;, and the pinch-off voltage Vp2 of the second FET is set to satisfy 0 >Vp2>&ggr;−&bgr;, where &agr;<&ggr;<&bgr;. A fixed potential &ggr; is applied to the gate of the second FET, and one of potentials &agr; and &bgr; is applied to the gate of the first FET, so that one of the first and second terminals can be electrically connected to the common terminal. Additional resonance and/or switching elements may be included as well.Type: GrantFiled: January 16, 2001Date of Patent: February 17, 2004Assignee: Murata Manufacturing Co. LtdInventors: Akihiro Sasabata, Shigekazu Okamoto, Motoyasu Nakao
-
Publication number: 20030183863Abstract: A field effect transistor (FET) is formed on a semiconductor substrate. A drain terminal, a source terminal, and a gate terminal connected to the FET are also formed on the semiconductor substrate. In an embodiment of the invention, a metal insulator metal (MIM) capacitor for blocking a bias current is disposed between the FET and the drain terminal. A bias terminal is provided between the MIM capacitor and the FET. Passive circuits connected to the drain terminal, the source terminal, and the gate terminal, and a bias circuit connected to the bias terminal are formed on a dielectric substrate. With this arrangement, the circuitry on the semiconductor substrate can be simplified. The general versatility of a resulting semiconductor device can be increased, and the size of the semiconductor device can be reduced.Type: ApplicationFiled: March 12, 2003Publication date: October 2, 2003Inventors: Motoyasu Nakao, Akihiro Sasabata
-
Publication number: 20020196098Abstract: A resonance type SPST switch is formed by connecting an inductive element in series with the drain of an FET, and then by connecting a capacitive element in parallel with the series connection of the FET and the inductive element. A constant-voltage source for feeding a voltage Vs is connected to the source of the FET, and a variable-voltage generator for switching the FET between an on state and a state in the vicinity of pinchoff is connected to the gate of the FET. When the variable-voltage generator feeds a voltage V&agr; in the vicinity of a pinchoff voltage to the gate of the FET, the SPST switch is closed while the amount of attenuation between first and second terminals is variably set. The resulting variable attenuator is thus compact in size, allows a large amount of attenuation to be set, and involves low manufacturing costs.Type: ApplicationFiled: April 2, 2002Publication date: December 26, 2002Applicant: Murata Manufacturing Company, Inc.Inventors: Akihiro Sasabata, Motoyasu Nakao
-
Patent number: 6496684Abstract: An SPST switch having a small transmission loss and a small power consumption is provided. The drain and the source of an FET are connected to each other in series through an induction element and a capacitor element, one terminal of the capacitor element is connected to a first terminal, the other terminal is connected to a second terminal, the gate of the FET is connected to a control terminal, the capacitance of the capacitor element is made equal to the OFF capacitance of the FET, and the inductance of the induction element is set to be such a value that the induction element resonates at a signal frequency with the capacitor element.Type: GrantFiled: July 11, 2001Date of Patent: December 17, 2002Assignee: Murata Manufacturing Co., Ltd.Inventors: Motoyasu Nakao, Akihiro Sasabata, Hiroaki Tanaka
-
Publication number: 20010049265Abstract: An SPST switch having a small transmission loss and a small power consumption is provided. The drain and the source of an FET are connected to each other in series through an induction element and a capacitor element, one terminal of the capacitor element is connected to a first terminal, the other terminal is connected to a second terminal, the gate of the FET is connected to a control terminal, the capacitance of the capacitor element is made equal to the OFF capacitance of the FET, and the inductance of the induction element is set to be such a value that the induction element resonates at a signal frequency with the capacitor element.Type: ApplicationFiled: July 11, 2001Publication date: December 6, 2001Applicant: Murata Manufacturing Co., Ltd.Inventors: Motoyasu Nakao, Akihiro Sasabata, Hiroaki Tanaka
-
Patent number: 6292067Abstract: An ASK modulator can be operated with only a positive-voltage power source. A source-voltage switching circuit that applies a positive voltage to the source of a FET when a data signal is at an L level in relation to the source of the FET is connected to the source of the FET which has a negative pinch-off voltage. Since the L level of the data signal can be set to 0 V, the ASK modulator can be configured only with the positive-voltage power source. This allows miniaturization and cost reduction to be implemented.Type: GrantFiled: April 28, 2000Date of Patent: September 18, 2001Assignee: Murata Manufacturing Co., Ltd.Inventors: Akihiro Sasabata, Shigekazu Okamoto, Motoyasu Nakao
-
Patent number: 6281762Abstract: An SPST switch having a small transmission loss and a small power consumption is provided. The drain and the source of an FET are connected to each other in series through an induction element and a capacitor element, one terminal of the capacitor element is connected to a first terminal, the other terminal is connected to a second terminal, the gate of the FET is connected to a control terminal, the capacitance of the capacitor element is made equal to the OFF capacitance of the FET, and the inductance of the induction element is set to be such a value that the induction element resonates at a signal frequency with the capacitor element.Type: GrantFiled: August 6, 1999Date of Patent: August 28, 2001Assignee: Murata Manufacturing Co., Ltd.Inventors: Motoyasu Nakao, Akihiro Sasabata, Hiroaki Tanaka