Abstract: To enable adjustment of digital filters suited to disturbances occurring in the surroundings. A receiving device includes: a digital filter that eliminates or attenuates a disturbance included in a signal received through a communication line; a coefficient adjusting unit that adjusts a coefficient of the digital filter based on operation schedule information of a device causing the disturbance in the communication line; and an information table that records a combination of operation information included in the operation schedule information and a coefficient of the digital filter corresponding to the operation information or correction information of the coefficient, in which the coefficient adjusting unit calculates the coefficient of the digital filter or the correction information of the coefficient from the information table based on the operation information included in the operation schedule information, and adjusts the coefficient of the digital filter.

Abstract: A PLC system includes a plurality of I/O devices each connecting a control target of each of a plurality of PLCs to each of the plurality of PLCs, and a PC. Each one of the plurality of PLCs stores first output data obtained by executing a self-assigned program to control the control target connected to each PLC, and stores second output data obtained when the PC or another PLC executes another program allocated to the PC or the other PLC to control the control target connected to the one PLC. Each of the plurality of PLCs outputs one of the first output data and the second output data to the I/O device connected to each PLC based on selection information transmitted from the PC.

Abstract: A programmable controller for executing a sequence program comprises a processor for reading and executing an instruction code from an external memory, an instruction cache memory for storing a branch destination program code of a branch instruction included in the sequence program, and a cache controller for entering the branch destination program code in the instruction cache memory according to data on priority, the instruction code of the branch instruction including the data on priority of an entry into the instruction cache memory.

Abstract: A PLC system includes a plurality of I/O devices each connecting a control target of each of a plurality of PLCs to each of the plurality of PLCs, and a PC. Each one of the plurality of PLCs stores first output data obtained by executing a self-assigned program to control the control target connected to each PLC, and stores second output data obtained when the PC or another PLC executes another program allocated to the PC or the other PLC to control the control target connected to the one PLC. Each of the plurality of PLCs outputs one of the first output data and the second output data to the I/O device connected to each PLC based on selection information transmitted from the PC.

Abstract: A programmable controller for executing a sequence program comprises a processor for reading and executing an instruction code from an external memory, an instruction cache memory for storing a branch destination program code of a branch instruction included in the sequence program, and a cache controller for entering the branch destination program code in the instruction cache memory according to data on priority, the instruction code of the branch instruction including the data on priority of an entry into the instruction cache memory.

Abstract: A programmable controller which executes a plurality of independent sequence programs in parallel is provided with an ASIC, including a plurality of arithmetic-logic units and a plurality of arbitration circuits, and MPUs as many as the arbitration circuits. The entire execution time of the programmable controller is shortened by changing combinations (groups of arithmetic-logic units) of the MPUs (and the arbitration circuits as many as the MPUs) and the arithmetic-logic units, based on the ratios of MPU execution instructions and ASIC execution instructions included in those instructions which constitute the programs to be executed in parallel.

Abstract: A programmable controller which executes a plurality of independent sequence programs in parallel is provided with an ASIC, including a plurality of arithmetic-logic units and a plurality of arbitration circuits, and MPUs as many as the arbitration circuits. The entire execution time of the programmable controller is shortened by changing combinations (groups of arithmetic-logic units) of the MPUs (and the arbitration circuits as many as the MPUs) and the arithmetic-logic units, based on the ratios of MPU execution instructions and ASIC execution instructions included in those instructions which constitute the programs to be executed in parallel.