Abstract: Method for testing an integrated circuit device, by defect modelling of the integrated circuit device, fault modelling of the integrated circuit device based on the information obtained from the defect modelling, test development based on information obtained from the fault modelling, and executing the test on the integrated circuit device. Defect modelling of the integrated circuit device including executing a physical defect analysis of the integrated circuit device to provide a set of effective technology parameters modified from a set of defect-free technology parameters associated with the integrated circuit device, and executing an electrical modelling of the integrated circuit device using the set of effective technology parameters to provide a defect-parametrized electrical model based on a defect-free electrical model of the integrated circuit device. The present methods allow parts-per-billion testing capabilities.

Abstract: Integrated circuit device having a processor module (2) in communication with a cache memory module (3, 4), and one or more memory control modules (6, 8, 10) each arranged to interface with an associated storage memory unit (5, 7, 9). An authentication module (15) is provided in communication with the memory control modules (6, 8, 10) and the cache memory modules (3, 4). The authentication module (15) is arranged to generate and store a hardware based secure key, read a predetermined set of data from the associated storage memory units (5, 7, 9), and an associated stored hash value, calculate a hash value of the predetermined set of data using the hardware based secure key; and store the predetermined set of data in the cache memory module (3, 4) only if the calculated hash value corresponds to the associated stored hash value.

Abstract: Method for testing an integrated circuit device (1), by defect modelling of the integrated circuit device (1), fault modelling of the integrated circuit device (1) based on the information obtained from the defect modelling, test development based on information obtained from the fault modelling, and executing the test on the integrated circuit device (1). Defect modelling of the integrated circuit device (1) comprises executing a physical defect analysis (10) of the integrated circuit device (1) to provide a set of effective technology parameters (Tpeff) modified from a set of defect-free technology parameters (Tpdf) associated with the integrated circuit device (1), and executing an electrical modelling (11) of the integrated circuit device (1) using the set of effective technology parameters (Tpeff) to provide a defect-parametrized electrical model (16; 17) based on a defect-free electrical model of the integrated circuit device (1). The present methods allow parts-per-billion testing capabilities.

Abstract: Integrated circuit device having a processor module (2) in communication with a cache memory module (3, 4), and one or more memory control modules (6, 8, 10) each arranged to interface with an associated storage memory unit (5, 7, 9). An authentication module (15) is provided in communication with the memory control modules (6, 8, 10) and the cache memory modules (3, 4). The authentication module (15) is arranged to generate and store a hardware based secure key, read a predetermined set of data from the associated storage memory units (5, 7, 9), and an associated stored hash value, calculate a hash value of the predetermined set of data using the hardware based secure key; and store the predetermined set of data in the cache memory module (3, 4) only if the calculated hash value corresponds to the associated stored hash value.

Abstract: Integrated circuit comprising one or more components (2; 2A-2G), each comprising embedded circuitry (21-31) allowing run-time execution of a micro-agent, and an interface to an agent network (4) (next to a data network (3) and a supply network (5)) interconnecting the one or more components (2; 2A-2G). The micro-agent is arranged to determine a signature of the associated component (2; 2A-2G), to communicate via the agent network (4) with further connected micro-agents being executed in further ones of the one or more components (2; 2A-2G) of the integrated circuit (1), and to detect a possible attack by analysing the determined signature.

Abstract: A computing device includes a computation circuit and a data storage circuit. The computation circuit is coupled to the data storage circuit and is arranged for reading and writing data from/to the data storage circuit. The computing device includes a memory array of non-volatile memory elements and controlling circuitry connected to the memory array for reading and writing data from/to selected memory elements in the array. The computation circuit and the data storage circuit are located in the memory array, and the non-volatile memory elements of the memory array are memristor-type elements.

Abstract: A computing device includes a computation circuit and a data storage circuit. The computation circuit is coupled to the data storage circuit and is arranged for reading and writing data from/to the data storage circuit. The computing device includes a memory array of non-volatile memory elements and controlling circuitry connected to the memory array for reading and writing data from/to selected memory elements in the array. The computation circuit and the data storage circuit are located in the memory array, and the non-volatile memory elements of the memory array are memristor-type elements.