Patents by Inventor Mou C. Lin
Mou C. Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7714608Abstract: In one embodiment, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. A sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.Type: GrantFiled: February 12, 2009Date of Patent: May 11, 2010Assignee: Lattice Semiconductor CorporationInventors: Mou C. Lin, William B. Andrews, John A. Schadt
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Patent number: 7605609Abstract: In one embodiment of the invention, a programmable level shifter can be selectively configured to operate in either a high-speed mode or a low-power mode. In both modes, the level shifter converts an input signal in one power supply domain into an output signal in another power supply domain. In the high-speed mode, p-type devices are configured as a current-mirror amplifier that provides the level shifter with relatively fast switching speed. In the low-power mode, the same p-type devices are configured as a cross-coupled latch that provides the level shifter with relatively low power consumption. Selectively enabled n-type devices provide the low-power mode with larger effective n-type devices to flip the cross-coupled latch formed by the p-type devices in the low-power mode.Type: GrantFiled: December 17, 2007Date of Patent: October 20, 2009Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Mou C. Lin, John Schadt
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Patent number: 7586325Abstract: In one embodiment, an integrated circuit has configurable application circuitry that operates at any one of multiple available power supply voltages. PT-control circuitry, operating at a PT reference voltage, generates a PT-control signal indicative of variations in process and temperature. Application-control circuitry controls the configuration of the application circuitry based on the selected power supply voltage for the application circuitry and the PT-control signal, where the selected power supply voltage is independent of the PT reference voltage.Type: GrantFiled: December 3, 2007Date of Patent: September 8, 2009Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Mou C. Lin, John Schadt
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Patent number: 7547995Abstract: In one embodiment of the invention, an integrated device has interface circuitry that includes a dynamic monitor that monitors the relative potential between (at least) two different power supplies to enable the device to react to over-voltage conditions such that appropriate selections can be made for which power supplies are selected for different components in the interface circuitry, such as output drivers and input receivers. The dynamic monitor enables over-voltage protection to be automatically implemented before the device has been configured, such as during the device's power-on state.Type: GrantFiled: February 2, 2006Date of Patent: June 16, 2009Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Larry R Fenstermaker, John A. Schadt, Mou C. Lin
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Patent number: 7495467Abstract: In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs.Type: GrantFiled: December 15, 2005Date of Patent: February 24, 2009Assignee: Lattice Semiconductor CorporationInventors: Mou C. Lin, William B. Andrews, John A. Schadt
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Patent number: 7443192Abstract: An improved output buffer having a digital output slew control and compensation for manufacturing process variations. Output slewing is accomplished by sequencing digital drive signals to paralleled output transistors. In one embodiment, a pre-driver sequences the drive signals by using the propagation delays of serially coupled digital logic gates to reduce power supply droop and/or ground bounce. The output transistors are turned off substantially simultaneously to avoid undesirable power supply DC current flow when the output buffer changes state. Programmably configuring the number of paralleled transistors that may be turned on at any given time allows a user to compensate for manufacturing process variations and determine the output impedance/drive capacity of the buffer.Type: GrantFiled: December 21, 2006Date of Patent: October 28, 2008Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Mou C. Lin, John A. Schadt
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Patent number: 7262630Abstract: In one embodiment of the invention, a programmable termination structure has first and second termination circuits for corresponding pads and a programmable connection therebetween. The first termination circuit supports first and second sets of termination schemes. A shared resistor is part of at least one termination scheme in each set. The first termination circuit supports a termination scheme between the first pad and a user-defined node connected to an on-chip capacitor such that first pad is connected via the termination scheme to the on-chip capacitor. Control circuitry automatically turns on and off a termination scheme for bidirectional signaling supported by the first termination circuit, wherein (1) the control circuitry turns off the termination scheme if an output buffer is configured to present outgoing signals at the first pad and (2) the control circuitry turns on the termination scheme if the output buffer is disabled in order to terminate incoming signals received at the first pad.Type: GrantFiled: August 1, 2005Date of Patent: August 28, 2007Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Barry K. Britton, John Schadt, Mou C. Lin
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Patent number: 7230810Abstract: An integrated circuit having a transistor device and over-voltage protection circuitry. The transistor device is implemented in a technology having a specified operating-voltage range, the transistor device having gate, drain, source, and tub nodes, and the specified operating-voltage range having a specified maximum voltage. The over-voltage protection circuitry is adapted to apply gate and tub voltages to the gate and tub nodes, respectively. If at least one channel voltage applied to at least one of the drain and source nodes exceeds the specified maximum voltage, then the over-voltage protection circuitry controls at least one of the gate voltage and the tub voltage to inhibit one or more adverse effects to the transistor device.Type: GrantFiled: December 9, 2004Date of Patent: June 12, 2007Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Mou C. Lin, Larry R. Fenstermaker
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Patent number: 7215149Abstract: An electrical system has a master circuit and an interface (I/F) circuit. The master circuit generates a master output signal. The I/F circuit receives an I/F input signal and a flag signal and generates an I/F output signal for application to a slave circuit, wherein the I/F input signal is based on the master output signal, and the interface circuit generates the L/F output signal either dependent on or independent of the I/F input signal as indicated by the flag signal.Type: GrantFiled: December 15, 2004Date of Patent: May 8, 2007Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Larry R. Fenstermaker, John Schadt, Mou C. Lin
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Patent number: 7161862Abstract: A memory sense amplifier includes an output and a complement output. The sense amplifier is configured such that a memory cell driving the bit line low enables latching of the bit line low by enabling pull-up of the complement output, and the memory cell driving the complement bit line low enables latching of the complement bit line low by enabling pull-up of the output.Type: GrantFiled: November 22, 2004Date of Patent: January 9, 2007Assignee: Lattice Semiconductor CorporationInventors: Mou C. Lin, Zheng Chen, Larry R. Fenstermaker
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Patent number: 7129749Abstract: A programmable logic device (PLD) having a programmable routing structure that employs non-static memory cells, such as dynamic random access memory (DRAM) cells, to control configurable circuit elements, such as pass-transistors and/or MUXes. In a representative embodiment, each DRAM cell is connected to its corresponding configurable circuit element using a buffer adapted to stabilize the output voltage generated by the cell and offset the effect of charge leakage from the cell capacitor. In addition, refresh circuitry associated with the DRAM cell periodically restores the charge in the cell capacitor using a refresh operation that is performed in the background, without disturbing the user functions of the PLD. Advantageously, a relatively large capacitance associated with a DRAM cell makes a PLD of the invention less susceptible to soft errors than a prior-art PLD that relies on SRAM cells for configuration control of its routing structure.Type: GrantFiled: October 27, 2004Date of Patent: October 31, 2006Assignee: Lattice Semiconductor CorporationInventors: Larry R. Fenstermaker, John A. Schadt, Mou C. Lin
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Patent number: 6967500Abstract: An electronic circuit with programmable terminations includes a circuit block, signal pads coupled to the circuit block, programmable termination circuits each associated with a corresponding one of the signal pads, and a reference circuit operative to generate one or more control signals for application to the programmable termination circuits. A given one of the programmable termination circuits is configurable independently of at least one of the other programmable termination circuits into one of a plurality of termination states. Preferably, the programmable termination circuits are each independently configurable to provide a particular termination resistance and a particular supply terminal connection type for the associated signal pad. The invention is particularly well suited for use in integrated circuit applications, such as, for example, those involving FPGAs, FPSCs and ASICs.Type: GrantFiled: March 26, 2003Date of Patent: November 22, 2005Assignee: Lattice Semiconductor CorporationInventors: Mou C. Lin, William Andrews, Arifur Rahman
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Patent number: 6943583Abstract: A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i.e., when the outgoing signal is not to be presented at that pad).Type: GrantFiled: September 25, 2003Date of Patent: September 13, 2005Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Mou C. Lin, Harold Scholz, Arifur Rahman
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Patent number: 6943582Abstract: A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i.e., when the outgoing signal is not to be presented at that pad).Type: GrantFiled: September 25, 2003Date of Patent: September 13, 2005Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Mou C. Lin, John Schadt
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Patent number: 6924659Abstract: A termination scheme for the I/O circuitry of a programmable device, such as a field-programmable gate array (FPGA), has programmable resistors switchably connected between reference voltages and two of the device's I/O pads and additional programmable resistors switchably connected between the two I/O pads. By appropriately controlling the reference voltages and the resistance levels, a single implementation of the termination scheme can be used to conform to a relatively wide variety of symmetric and non-symmetric complementary and differential signaling applications.Type: GrantFiled: July 28, 2003Date of Patent: August 2, 2005Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Mou C. Lin
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Patent number: 6859066Abstract: A bank of input/output buffers are configured such that each input buffer in the bank may select from a plurality of voltage references during single-ended operation. Similarly, the pad associated with each input buffer may serve to supply one of the voltage references for other input buffers within the bank.Type: GrantFiled: February 28, 2003Date of Patent: February 22, 2005Assignee: Lattice Semiconductor CorporationInventors: Arifur Rahman, William Andrews, Mou C. Lin