Patents by Inventor Mou Lin

Mou Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Temperature-independent, linear on-chip termination resistance
    Publication number: 20070164844
    Abstract: In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs.
    Type: Application
    Filed: December 15, 2005
    Publication date: July 19, 2007
    Inventors: Mou Lin, William Andrews, John Schadt
  • High performance system-on-chip discrete components using post passivation process
    Publication number: 20050230783
    Abstract: A system and method for forming post passivation discrete components, is described. High quality discrete components are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.
    Type: Application
    Filed: February 18, 2005
    Publication date: October 20, 2005
    Inventor: Mou Lin