Patents by Inventor Mou-Shiung Lin

Mou-Shiung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210104551
    Abstract: A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC c
    Type: Application
    Filed: November 22, 2020
    Publication date: April 8, 2021
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20210090983
    Abstract: A chip package includes a first interconnection scheme; a plurality of first metal contacts under and on the first interconnection scheme and at a bottom surface of the chip package; a first semiconductor IC chip over the first interconnection scheme; a first connector over the first interconnection scheme and at a same horizontal level as the first semiconductor IC chip, wherein the first connector comprises a first substrate and a plurality of first through vias vertically extending through the first substrate of the first connector; a first polymer layer over the first interconnection scheme, wherein the first polymer layer has a top surface coplanar with a top surface of the first semiconductor IC chip, a top surface of the first substrate of the first connector and a top surface of each of the plurality of first through vias; and a second interconnection scheme on the top surface of the first polymer layer, the top surface of the first semiconductor IC chip, the top surface of the first connector and the
    Type: Application
    Filed: September 19, 2020
    Publication date: March 25, 2021
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 10957679
    Abstract: A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: March 23, 2021
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Publication number: 20210075423
    Abstract: A three-dimensional programmable interconnection system based on a multi-chip package includes: a programmable metal bump or pad at a bottom of the multi-chip package; a first programmable interconnect provided by an interposer of the multi-chip package; a second programmable interconnect provided by the interposer; and a switch provided by a first semiconductor chip of the multi-chip package, wherein the switch is configured to control connection between the first and second programmable interconnects, wherein the programmable metal bump or pad couples to a second semiconductor chip of the multi-chip package through the switch and the first and second programmable interconnects, wherein the first and second semiconductor chips are over the interposer.
    Type: Application
    Filed: November 17, 2020
    Publication date: March 11, 2021
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 10937762
    Abstract: A multi-chip package comprising: an interconnection substrate comprising an interconnection bridge embedded in the interconnection substrate, and an interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection layer and the interconnection bridge, and a polymer layer between the first and second interconnection metal layers, wherein the interconnection bridge is embedded in the interconnection scheme and has sidewalls surrounded by the polymer layer; a semiconductor IC chip over the interconnection substrate and across over an edge of the interconnection bridge; a memory chip over the interconnection substrate and across over an edge of the interconnection bridge, wherein the interconnection bridge comprises a plurality of metal interconnects configured for a data bus coupling the semiconductor IC chip to the memory chip, wherein a bitwidth of the data bus between the semiconductor IC chip and the memory chip is greater than or equa
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: March 2, 2021
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20210050300
    Abstract: A multichip package includes: a chip package comprising a first IC chip, a polymer layer in a space beyond and extending from a sidewall of the first IC chip, a through package via in the polymer layer, an interconnection scheme under the first IC chip, polymer layer and through package via, and a metal bump under the interconnection scheme and at a bottom of the chip package, wherein the first IC chip comprises memory cells for storing data therein associated with resulting values for a look-up table (LUT) and a selection circuit comprising a first input data set for a logic operation and a second input data set associated with the data stored in the memory cells, wherein the selection circuit selects, in accordance with the first input data set, data from the second input data set as an output data for the logic operation; and a second IC chip over the chip package, wherein the second IC chip couples to the first IC chip through, in sequence, the through package via and interconnection scheme, wherein the s
    Type: Application
    Filed: November 4, 2020
    Publication date: February 18, 2021
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20210043557
    Abstract: A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top sur
    Type: Application
    Filed: August 4, 2020
    Publication date: February 11, 2021
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Publication number: 20210035295
    Abstract: A method for obtaining a probability in a 3D probability map, includes: obtaining at least one value of at least one parameter for each stop of a 3D moving window, wherein a first, second, third and fourth of the stops are partially overlapped, the first and second stops are shifted from each other by a distance equal to a first dimension of a computation voxel, the first and third stops are shifted from each other by a distance equal to a second dimension of the computation voxel, and the first and fourth stops are shifted from each other by a distance equal to a third dimension of the computation voxel; matching the at least one value to a classifier to obtain a first probability for each stop of the 3D moving window; and calculating a second probability for the computation voxel based on information associated with the first probabilities for the first through fourth stops.
    Type: Application
    Filed: October 18, 2020
    Publication date: February 4, 2021
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 10892011
    Abstract: A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC c
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: January 12, 2021
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20210005592
    Abstract: A multichip package comprising: a first chip package comprising a first semiconductor IC chip, a first polymer layer in a space beyond and extending from a sidewall of the first semiconductor IC chip, a first through package via in the first polymer layer, and a first interconnection scheme under the first semiconductor IC chip, first polymer layer and first through package via, wherein the first semiconductor IC chip comprises a plurality of volatile memory cells configured to store first data associated with a plurality of resulting values for a look-up table (LUT) and a selection circuit configured to select, in accordance with a first input data set thereof, a data from a second input data set thereof as an output data for the logic operation; a first metal bump under the first chip package; and a non-volatile memory IC chip over the first chip package, wherein the non-volatile memory IC chip comprises a plurality of first non-volatile memory cells configured to store second data associated with the plura
    Type: Application
    Filed: July 1, 2020
    Publication date: January 7, 2021
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 10886924
    Abstract: A three-dimensional programmable interconnection system based on a multi-chip package includes: a programmable metal bump or pad at a bottom of the multi-chip package; a first programmable interconnect provided by an interposer of the multi-chip package; a second programmable interconnect provided by the interposer; and a switch provided by a first semiconductor chip of the multi-chip package, wherein the switch is configured to control connection between the first and second programmable interconnects, wherein the programmable metal bump or pad couples to a second semiconductor chip of the multi-chip package through the switch and the first and second programmable interconnects, wherein the first and second semiconductor chips are over the interposer.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: January 5, 2021
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20200403617
    Abstract: A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 24, 2020
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 10872413
    Abstract: A method for obtaining a probability in a 3D probability map, includes: obtaining at least one value of at least one parameter for each stop of a 3D moving window, wherein a first, second, third and fourth of the stops are partially overlapped, the first and second stops are shifted from each other by a distance equal to a first dimension of a computation voxel, the first and third stops are shifted from each other by a distance equal to a second dimension of the computation voxel, and the first and fourth stops are shifted from each other by a distance equal to a third dimension of the computation voxel; matching the at least one value to a classifier to obtain a first probability for each stop of the 3D moving window; and calculating a second probability for the computation voxel based on information associated with the first probabilities for the first through fourth stops.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: December 22, 2020
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 10819345
    Abstract: A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: October 27, 2020
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Publication number: 20200313675
    Abstract: A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.
    Type: Application
    Filed: June 13, 2020
    Publication date: October 1, 2020
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 10727837
    Abstract: A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: July 28, 2020
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Publication number: 20200235740
    Abstract: An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.
    Type: Application
    Filed: March 16, 2020
    Publication date: July 23, 2020
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Publication number: 20200228120
    Abstract: A three-dimensional programmable interconnection system based on a multi-chip package includes: a programmable metal bump or pad at a bottom of the multi-chip package; a first programmable interconnect provided by an interposer of the multi-chip package; a second programmable interconnect provided by the interposer; and a switch provided by a first semiconductor chip of the multi-chip package, wherein the switch is configured to control connection between the first and second programmable interconnects, wherein the programmable metal bump or pad couples to a second semiconductor chip of the multi-chip package through the switch and the first and second programmable interconnects, wherein the first and second semiconductor chips are over the interposer.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20200212914
    Abstract: A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.
    Type: Application
    Filed: March 13, 2020
    Publication date: July 2, 2020
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Publication number: 20200186151
    Abstract: A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.
    Type: Application
    Filed: February 14, 2020
    Publication date: June 11, 2020
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin