Patents by Inventor Mouli Rajaram Chollangi
Mouli Rajaram Chollangi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11624777Abstract: Various implementations described herein are related to a method for constructing integrated circuitry and identifying input signal paths, internal signal paths and output signal paths associated with the integrated circuitry. The method may include generating a timing table for slew-load characterization of the input signal paths, the internal signal paths and the output signal paths. The method may include simulating corner points for the timing table, building diagonal points for the timing table based on the simulated corner points, and building remaining points for the timing table based on the simulated corner points and the diagonal points.Type: GrantFiled: April 23, 2020Date of Patent: April 11, 2023Assignee: Arm LimitedInventors: Sriram Thyagarajan, Pratik Ghanshambhai Satasia, Yew Keong Chong, Andy Wangkun Chen, Mouli Rajaram Chollangi
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Patent number: 11567741Abstract: Various implementations described herein are directed to a system and methods for memory compiling. For instance, a method may include selecting source corners from a memory compiler configuration and generating a standardized set of memory instances for the selected source corners. Also, the method may include deriving a reduced set of memory instances based on the standardized set of memory instances and building a memory compiler database for a compiler space based on the standardized set of memory instances and the reduced set of memory instances.Type: GrantFiled: June 11, 2020Date of Patent: January 31, 2023Assignee: Arm LimitedInventors: Mouli Rajaram Chollangi, Sriram Thyagarajan, Hongwei Zhu, Yew Keong Chong, Pratik Ghanshambhai Satasia
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Publication number: 20210389934Abstract: Various implementations described herein are directed to a system and methods for memory compiling. For instance, a method may include selecting source corners from a memory compiler configuration and generating a standardized set of memory instances for the selected source corners. Also, the method may include deriving a reduced set of memory instances based on the standardized set of memory instances and building a memory compiler database for a compiler space based on the standardized set of memory instances and the reduced set of memory instances.Type: ApplicationFiled: June 11, 2020Publication date: December 16, 2021Inventors: Mouli Rajaram Chollangi, Sriram Thyagarajan, Hongwei Zhu, Yew Keong Chong, Pratik Ghanshambhai Satasia
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Publication number: 20210333320Abstract: Various implementations described herein are related to a method for constructing integrated circuitry and identifying input signal paths, internal signal paths and output signal paths associated with the integrated circuitry. The method may include generating a timing table for slew-load characterization of the input signal paths, the internal signal paths and the output signal paths. The method may include simulating corner points for the timing table, building diagonal points for the timing table based on the simulated corner points, and building remaining points for the timing table based on the simulated corner points and the diagonal points.Type: ApplicationFiled: April 23, 2020Publication date: October 28, 2021Inventors: Sriram Thyagarajan, Pratik Ghanshambhai Satasia, Yew Keong Chong, Andy Wangkun Chen, Mouli Rajaram Chollangi
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Patent number: 10579775Abstract: Various implementations described herein are directed to a method that identifies a memory instance with multiple tile-cells. The memory instance has memory instance leakage data, and each tile-cell of the multiple tile-cells has tile-cell leakage data. The method subdivides the multiple tile-cells into multiple categories based on a relationship between the memory instance leakage data and the tile-cell leakage data. The method obtains measured leakage data for each tile-cell of the multiple tile-cells by simulating the memory instance based on the memory instance leakage data and the tile-cell leakage data for each category of the multiple categories. The method determines a combined leakage of the memory instance by combining the measured leakage data for each tile-cell of the multiple tile-cells.Type: GrantFiled: July 11, 2018Date of Patent: March 3, 2020Assignee: Arm LimitedInventors: Vincent Philippe Schuppe, Syam Kumar Lalitha Gopalakrishnan Nair, Hongwei Zhu, Neeraj Dogra, Mouli Rajaram Chollangi, Arjun R. Prasad
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Publication number: 20200019669Abstract: Various implementations described herein are directed to a method that identifies a memory instance with multiple tile-cells. The memory instance has memory instance leakage data, and each tile-cell of the multiple tile-cells has tile-cell leakage data. The method subdivides the multiple tile-cells into multiple categories based on a relationship between the memory instance leakage data and the tile-cell leakage data. The method obtains measured leakage data for each tile-cell of the multiple tile-cells by simulating the memory instance based on the memory instance leakage data and the tile-cell leakage data for each category of the multiple categories. The method determines a combined leakage of the memory instance by combining the measured leakage data for each tile-cell of the multiple tile-cells.Type: ApplicationFiled: July 11, 2018Publication date: January 16, 2020Inventors: Vincent Philippe Schuppe, Syam Kumar Lalitha Gopalakrishnan Nair, Hongwei Zhu, Neeraj Dogra, Mouli Rajaram Chollangi, Arjun R. Prasad
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Patent number: 10521532Abstract: Various implementations described herein refer to a method. The method may include selecting a target memory instance to characterize for timing file generation, determining a number of segments for the target memory instance based on user defined accuracy, and partitioning the target memory instance into the number of segments based on a physical architecture of the target memory instance. The method may also include generating test-bench data based on the number of segments and simulating the test-bench data, obtaining simulation data for the target memory instance associated with each segment in the number of segments, and generating a timing file by reporting timing data for each segment in the number of segments.Type: GrantFiled: September 7, 2018Date of Patent: December 31, 2019Assignee: Arm LimitedInventors: Pratik Ghanshambhai Satasia, Yew Keong Chong, Sriram Thyagarajan, Hongwei Zhu, Mouli Rajaram Chollangi
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Patent number: 10296688Abstract: A silicon compiler, such as a memory compiler, provides for pin-based noise characterization in a computationally efficient manner. For a given user-provided option set, a silicon compiler provides a noise database for the set of all available memory instances by performing pin-based noise characterization on only a subset of the set of available memory instances.Type: GrantFiled: December 21, 2016Date of Patent: May 21, 2019Assignee: ARM LimitedInventors: Mouli Rajaram Chollangi, Hongwei Zhu, Hemant Joshi, Chandan Kumar Rajendran, Prashant Lokeshwar, Umang Deepak kumar Doshi, Neeraj Dogra
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Patent number: 10140399Abstract: Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. The mapper module may include a decision making engine that decides fabrication parameters for building the destination corner database based on the verified user configuration input and memory compiler metadata. The computing device may include a builder module that performs a simulation of the destination corner based on the fabrication parameters, collects simulation results data associated with the simulation, and builds the destination corner database for the destination corner based on the simulation results data and source corner data.Type: GrantFiled: December 21, 2016Date of Patent: November 27, 2018Assignee: ARM LimitedInventors: Hongwei Zhu, Mouli Rajaram Chollangi, Hemant Joshi, Yew Keong Chong, Satinderjit Singh, Betsie Jacob, Neeraj Dogra, Sriram Thyagarajan
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Publication number: 20180173822Abstract: Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. The mapper module may include a decision making engine that decides fabrication parameters for building the destination corner database based on the verified user configuration input and memory compiler metadata. The computing device may include a builder module that performs a simulation of the destination corner based on the fabrication parameters, collects simulation results data associated with the simulation, and builds the destination corner database for the destination corner based on the simulation results data and source corner data.Type: ApplicationFiled: December 21, 2016Publication date: June 21, 2018Inventors: Hongwei Zhu, Mouli Rajaram Chollangi, Hemant Joshi, Yew Keong Chong, Satinderjit Singh, Betsie Jacob, Neeraj Dogra, Sriram Thyagarajan
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Publication number: 20180173834Abstract: A silicon compiler, such as a memory compiler, provides for pin-based noise characterization in a computationally efficient manner. For a given user-provided option set, a silicon compiler provides a noise database for the set of all available memory instances by performing pin-based noise characterization on only a subset of the set of available memory instances.Type: ApplicationFiled: December 21, 2016Publication date: June 21, 2018Inventors: Mouli Rajaram Chollangi, Hongwei Zhu, Hemant Joshi, Chandan Kumar Rajendran, Prashant Lokeshwar, Umang Deepak Kumar Doshi, Neeraj Dogra