Patents by Inventor Mouloud Bakli

Mouloud Bakli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6677254
    Abstract: The formation of a barrier layer over a high k dielectric layer and deposition of a conducting layer over the barrier layer prevents intermigration between the species of the high k dielectric layer and the conducting layer and prevents oxygen scavenging of the high k dielectric layer. One example of a capacitor stack device provided includes a high k dielectric layer of Ta2O5, a barrier layer of TaON or TiON formed at least in part by a remote plasma process, and a top electrode of TiN. The processes may be conducted at about 300 to 700° C. and are thus useful for low thermal budget applications. Also provided are MIM capacitor constructions and methods in which an insulator layer is formed by remote plasma oxidation of a bottom electrode.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: January 13, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Pravin Narwankar, Mouloud Bakli, Ravi Rajagopalan, Randall S. Urdahl, Asher Sinensky, Shankarram Athreya
  • Patent number: 6638810
    Abstract: The invention provides a method for forming a metal nitride film by depositing a metal oxide film on the substrate and exposing the metal oxide film to a nitrating gas to densify the metal oxide and form a metal nitride film. The metal oxide film is deposited by the decomposition of a chemical vapor deposition precursor. The nitrating step comprises exposing the metal oxide film to a thermally or plasma enhanced nitrating gas preferably comprising nitrogen, oxygen, and ammonia. The invention also provides a process for forming a liner/barrier scheme for a metallization stack by forming a metal nitride layer over the substrate by the densification of a metal oxide layer by a nitrating gas depositing a metal liner layer. Optionally, a metal liner layer may be deposited over substrate prior to the metal nitride layer to forma metal/metal nitride liner/barrier scheme.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: October 28, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Mouloud Bakli, Steve G. Ghanayem, Huyen T. Tran
  • Patent number: 6524954
    Abstract: A method for reducing the resistivity in a gate electrode is described. In one embodiment of the present invention, a silicon layer is formed on a substrate. A tungsten silicide layer is then formed on the silicon layer. The tungsten silicide layer is implanted with boron ions and an anneal is performed. The tungsten silicide layer and silicon layer are then patterned to form a gate electrode.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: February 25, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Mouloud Bakli, Herve Monchoix, Denis Sauvage
  • Publication number: 20030025146
    Abstract: The formation of a barrier layer over a high k dielectric layer and deposition of a conducting layer over the barrier layer prevents intermigration between the species of the high k dielectric layer and the conducting layer and prevents oxygen scavenging of the high k dielectric layer. One example of a capacitor stack device provided includes a high k dielectric layer of Ta2O5, a barrier layer of TaON or TiON formed at least in part by a remote plasma process, and a top electrode of TiN. The processes may be conducted at about 300 to 700° C. and are thus useful for low thermal budget applications. Also provided are MIM capacitor constructions and methods in which an insulator layer is formed by remote plasma oxidation of a bottom electrode.
    Type: Application
    Filed: July 23, 2001
    Publication date: February 6, 2003
    Inventors: Pravin Narwankar, Mouloud Bakli, Ravi Rajagopalan, Randall S. Urdahl, Asher Sinensky, Shankarram Athreya
  • Publication number: 20030008501
    Abstract: The invention provides a method for forming a metal nitride film by depositing a metal oxide film on the substrate and exposing the metal oxide film to a nitrating gas to densify the metal oxide and form a metal nitride film. The metal oxide film is deposited by the decomposition of a chemical vapor deposition precursor. The nitrating step comprises exposing the metal oxide film to a thermally or plasma enhanced nitrating gas preferably comprising nitrogen, oxygen, and ammonia. The invention also provides a process for forming a liner/barrier scheme for a metallization stack by forming a metal nitride layer over the substrate by the densification of a metal oxide layer by a nitrating gas depositing a metal liner layer. Optionally, a metal liner layer may be deposited over substrate prior to the metal nitride layer to forma metal/metal nitride liner/barrier scheme.
    Type: Application
    Filed: November 5, 2001
    Publication date: January 9, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Mouloud Bakli, Steve G. Ghanayem, Huyen T. Tran
  • Patent number: 6319766
    Abstract: The invention provides a method for forming a metal nitride film by depositing a metal oxide film on the substrate and exposing the metal oxide film to a nitrating gas to densify the metal oxide and form a metal nitride film. The metal oxide film is deposited by the decomposition of a chemical vapor deposition precursor. The nitrating step comprises exposing the metal oxide film to a thermally or plasma enhanced nitrating gas preferably comprising nitrogen, oxygen, and anunonia. The invention also provides a process for forming a liner/barrier scheme for a metallization stack by forming a metal nitride layer over the substrate by the densification of a metal oxide layer by a nitrating gas depositing a metal liner layer. Optionally, a metal liner layer may be deposited over substrate prior to the metal nitride layer to form a metal/metal nitride liner/barrier scheme.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: November 20, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Mouloud Bakli, Steve G. Ghanayem, Huyen T. Tran
  • Patent number: 5300455
    Abstract: An integrated circuit such as a MOS transistor, having an electrically conductive diffusion barrier at the metal/silicon interface and a method of manufacture therefor is disclosed. The metal/silicon interface is formed by selective metal deposition onto silicon. According to the method, the interface is subjected to a nitrogen-based plasma during a period of at least five minutes. The interface is brought to a temperature greater than 500.degree. C. during this period, in order to create a diffusion barrier comprising a silicon nitride layer. The interface is then subjected to an annealing treatment under a neutral atmosphere so as to remove the nitrogen previously introduced into the metal. The diffusion barrier forms a linking and protecting interface between each source drain or gate zone of the MOS transistor and the corresponding layer of metal covering the latter.
    Type: Grant
    Filed: December 13, 1991
    Date of Patent: April 5, 1994
    Assignee: France Telecom
    Inventors: Bernard Vuillermoz, Mouloud Bakli, Alain Straboni