Abstract: An apparatus is disclosed for dual-mode amplification by varying a load impedance. In an example aspect, the apparatus includes a low-noise amplifier, a first component, a second component, and a switch. The first component has a first input impedance. The second component is coupled between the low-noise amplifier and the first component. The second component has a second input impedance that is greater than the first input impedance. The switch is coupled in parallel with the second component between the low-noise amplifier and the first component. The switch is configured to selectively be in an open state to engage the second component or a closed state to bypass the second component.

Abstract: An apparatus includes: a first amplifier stage configured to receive an input signal through a first gate inductor and a first source inductor; and a second amplifier stage configured to receive the input signal through the first gate inductor in series with a second gate inductor and the first source inductor in series with a second source inductor.

Abstract: A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

Abstract: Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.

Abstract: Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

Abstract: Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

Abstract: An oscillator, including amplifier circuitry and resonant circuitry, for providing an oscillation signal with a controllable frequency while maintaining a substantially constant steady state magnitude. Controllable reactive circuitry, included as part of the amplifier circuitry, has a reactance which can be controlled such that the resistive components of the amplifier circuitry and resonant circuitry impedances remain substantially equal. When in the form of serially coupled, controllable capacitances, the controllable reactive circuitry is controlled such that a ratio of changes in the controllable capacitances is approximately equal to a negative ratio of the capacitance values.

Abstract: Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.