Patents by Inventor Mounir Fares
Mounir Fares has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10862425Abstract: Techniques are described for tuning a resonant circuit using differential switchable capacitors. For example, embodiments can operate in context of a power amplifier with a tunable resonant output network. To tune the network, multiple differential switchable capacitors are provided in parallel. Each differential switchable capacitor can include a pair of capacitors, each coupled between a respective internal node and a respective differential terminal; and the internal nodes are selectively coupled or decoupled using a respective electronic switch (e.g., transistor). Switching on one of the differential switchable capacitors forms a capacitive channel having an associated capacitance. Each differential switchable capacitor can also include a switch network to selectively pull the internal nodes to a high or low voltage reference according to the selected operating mode.Type: GrantFiled: April 25, 2019Date of Patent: December 8, 2020Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.Inventors: Ahmed Emira, Mounir Fares
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Publication number: 20200343857Abstract: Techniques are described for tuning a resonant circuit using differential switchable capacitors. For example, embodiments can operate in context of a power amplifier with a tunable resonant output network. To tune the network, multiple differential switchable capacitors are provided in parallel. Each differential switchable capacitor can include a pair of capacitors, each coupled between a respective internal node and a respective differential terminal; and the internal nodes are selectively coupled or decoupled using a respective electronic switch (e.g., transistor). Switching on one of the differential switchable capacitors forms a capacitive channel having an associated capacitance. Each differential switchable capacitor can also include a switch network to selectively pull the internal nodes to a high or low voltage reference according to the selected operating mode.Type: ApplicationFiled: April 25, 2019Publication date: October 29, 2020Inventors: Ahmed EMIRA, Mounir FARES
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Patent number: 9065476Abstract: A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices.Type: GrantFiled: May 6, 2013Date of Patent: June 23, 2015Assignee: Texas Instruments IncorporatedInventors: Rahmi Hezar, Baher Haroun, Halil Kiper, Mounir Fares, Ajay Kumar
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Publication number: 20130241758Abstract: A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices.Type: ApplicationFiled: May 6, 2013Publication date: September 19, 2013Applicant: Texas Instruments IncorporatedInventors: Rahmi Hezar, Baher Haroun, Halil Kiper, Mounir Fares, Ajay Kumar
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Patent number: 8456341Abstract: A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices.Type: GrantFiled: June 3, 2011Date of Patent: June 4, 2013Assignee: Texas Instruments IncorporatedInventors: Rahmi Hezar, Baher Haroun, Halil Kiper, Mounir Fares, Ajay Kumar
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Publication number: 20120306678Abstract: A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices.Type: ApplicationFiled: June 3, 2011Publication date: December 6, 2012Inventors: Rahmi Hezar, Baher Haroun, Halil Kiper, Mounir Fares, Ajay Kumar
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Patent number: 6804697Abstract: An averaging circuit includes: input signal nodes for providing input signals 330; a multiplexing circuit 320 coupled to the input signal nodes for switching between the input signals 330 to create a time waveform; a low pass filter 300 coupled to an output 340 of the multiplexing circuit 320 for filtering the time waveform to create an average signal; and an average replication circuit 310 coupled to an output 350 of the low pass filter 300.Type: GrantFiled: July 13, 2001Date of Patent: October 12, 2004Assignee: Texas Instruments IncorporatedInventors: Alexander Bugeja, Ching-yuh Tsay, Irfan A. Chaudhry, Mounir Fares
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Patent number: 6424283Abstract: A segmented digital-to-analog converter includes: upper segments 200, 210, and 220; a thermometer decoder 400; a randomizing circuit 410 coupled between the thermometer decoder 400 and the upper segments 200, 210, and 220 for randomizing an output of the thermometer decoder 400; a divider location selector circuit 420 coupled between the randomizing circuit 410 and the upper segments 200, 210, and 220 for choosing a selected segment from the upper segments 200, 210, and 220; and lower segments 225 coupled to the selected segment.Type: GrantFiled: July 13, 2001Date of Patent: July 23, 2002Assignee: Texas Instruments IncorporatedInventors: Alexander Bugeja, Ching-yuh Tsay, Irfan A. Chaudhry, Mounir Fares
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Publication number: 20020026469Abstract: An averaging circuit includes: input signal nodes for providing input signals 330; a multiplexing circuit 320 coupled to the input signal nodes for switching between the input signals 330 to create a time waveform; a low pass filter 300 coupled to an output 340 of the multiplexing circuit 320 for filtering the time waveform to create an average signal; and an average replication circuit 310 coupled to an output 350 of the low pass filter 300.Type: ApplicationFiled: July 13, 2001Publication date: February 28, 2002Inventors: Alexander Bugeja, Ching-yuh Tsay, Irfan A. Chaudhry, Mounir Fares
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Publication number: 20020008651Abstract: A segmented digital-to-analog converter includes: upper segments 200, 210, and 220; a thermometer decoder 400; a randomizing circuit 410 coupled between the thermometer decoder 400 and the upper segments 200, 210, and 220 for randomizing an output of the thermometer decoder 400; a divider location selector circuit 420 coupled between the randomizing circuit 410 and the upper segments 200, 210, and 220 for choosing a selected segment from the upper segments 200, 210, and 220; and lower segments 225 coupled to the selected segment.Type: ApplicationFiled: July 13, 2001Publication date: January 24, 2002Inventors: Alexander Bugeja, Ching-yuh Tsay, Irfan A. Chaudhry, Mounir Fares
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Publication number: 20010045902Abstract: A differential switching circuit includes: a first inverter 46; a first pull-up transistor 43 coupled between the first inverter 46 and a high-side power supply node; a first pull-down transistor 34 coupled between the first inverter 46 and a low-side power supply node; an output node of the first inverter 46 coupled to a control node of the first pull-up transistor 43 and a control node of the first pull-down transistor 34; a second inverter 47; a second pull-up transistor 45 coupled between the second inverter 47 and the high-side power supply node; a second pull-down transistor 36 coupled between the second inverter 47 and the low-side power supply node; and an output node of the second inverter 47 coupled to a control node of the second pull-up transistor 45 and a control node of the second pull-down transistor 36, wherein the first and second inverters 46 and 47 are coupled together between the inverters and the pull-up transistors 43 and 45, and between the inverters and the pull-down transistors 34 andType: ApplicationFiled: January 31, 2001Publication date: November 29, 2001Inventors: Irfan A. Chaudhry, Abdellatif Bellaouar, Mounir Fares, Eric G. Soenen
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Patent number: 6310569Abstract: A skewless differential switching circuit uses skewless switching elements to convert complementary signals with skew into complementary output signals with minimal time skew between the output signals and with equalized rise and fall times of the output signals for minimum harmonic distortion.Type: GrantFiled: January 31, 2001Date of Patent: October 30, 2001Assignee: Texas Instruments IncorporatedInventors: Irfan A. Chaudhry, Abdellatif Bellaouar, Mounir Fares, Eric G. Soenen