Abstract: The present invention involves a method of controlling at least one first element (22) for heating a multi-resonant optical device (10), automatically alternating between at least a first mode and a second mode, wherein, in the first mode, the first heating element is controlled by a first feedback loop (20) to lead the optical device to operate at a first resonance peak and wherein, at least during part of the second mode, the first feedback loop is made diverging to lead the optical device to operate at a second resonance peak.

Abstract: An optical arbiter device, between conflicting access requests to a shared resource sent by N processing nodes of a network-on-chip system, comprising at least one primary optical arbiter bus, at least one optical source for transmitting a first optical signal in said at least one primary optical arbiter bus, and a sequence of N optical arbiter cells coupled with the primary optical arbiter bus, each of these optical arbiter cells being associated with a processing node and having means for selecting the processing node with which said each optical arbiter cell is associated by re-routing the first optical signal. The optical source is designed to transmit a second optical signal propagated in an opposite direction to the first optical signal along the primary optical arbiter bus. Furthermore, the selection means of each optical arbiter cell are designed to perform said selection by re-routing the first and second optical signals.

Abstract: The present invention involves a method of controlling at least one first element (22) for heating a multi-resonant optical device (10), automatically alternating between at least a first mode and a second mode, wherein, in the first mode, the first heating element is controlled by a first feedback loop (20) to lead the optical device to operate at a first resonance peak and wherein, at least during part of the second mode, the first feedback loop is made diverging to lead the optical device to operate at a second resonance peak.

Abstract: An optical arbiter device, between conflicting access requests to a shared resource sent by N processing nodes of a network-on-chip system, comprising at least one primary optical arbiter bus, at least one optical source for transmitting a first optical signal in said at least one primary optical arbiter bus, and a sequence of N optical arbiter cells coupled with the primary optical arbiter bus, each of these optical arbiter cells being associated with a processing node and having means for selecting the processing node with which said each optical arbiter cell is associated by re-routing the first optical signal. The optical source is designed to transmit a second optical signal propagated in an opposite direction to the first optical signal along the primary optical arbiter bus. Furthermore, the selection means of each optical arbiter cell are designed to perform said selection by re-routing the first and second optical signals.

Abstract: A deserializer circuit includes demultiplexer circuitry configured to receive serial data from an input and output a plurality of divided data outputs, and multiplexer circuitry configured to receive a first logic level at a first input of said multiplexer circuitry, and receive a second logic level at a second input of said multiplexer circuitry and receive one of said divided data outputs at a control input of said multiplexer circuitry. The outputs of the multiplexer circuitry produce the received serial data in a parallel form.

Abstract: A clock gate includes a first Muller gate that receives at its inputs a clock signal and an enable signal. The output of the first Muller gate is applied, with a delayed version of the clock signal, to a second Muller gate. A logic circuit operates to logically combine the output of the second Muller gate with a delayed version of the clock signal. The output of the logic circuit provides a gated clock output.

Abstract: A deserializer circuit includes demultiplexer circuitry configured to receive serial data from an input and output a plurality of divided data outputs, and multiplexer circuitry configured to receive a first logic level at a first input of said multiplexer circuitry, and receive a second logic level at a second input of said multiplexer circuitry and receive one of said divided data outputs at a control input of said multiplexer circuitry. The outputs of the multiplexer circuitry produce the received serial data in a parallel form.

Abstract: A clock gate includes a first Muller gate that receives at its inputs a clock signal and an enable signal. The output of the first Muller gate is applied, with a delayed version of the clock signal, to a second Muller gate. A logic circuit operates to logically combine the output of the second Muller gate with a delayed version of the clock signal. The output of the logic circuit provides a gated clock output.