Patents by Inventor Mousa H. Ishaq
Mousa H. Ishaq has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9847213Abstract: A vacuum trap, a plasma etch system using the vacuum trap and a method of cleaning the vacuum trap. The vacuum trap includes a baffle housing; and a removable baffle assembly disposed in the baffle housing, the baffle assembly comprising a set of baffle plates, the baffle plates spaced along a support rod from a first baffle plate to a last baffle plate, the baffle plates alternately disposed above and below the support rod and alternately disposed in an upper region and a lower region of the baffle housing.Type: GrantFiled: May 28, 2015Date of Patent: December 19, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Joseph K. Comeau, David R. Crawford, Robert E. Desrosiers, Tracy C. Hetrick, Mousa H. Ishaq
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Patent number: 9168571Abstract: A method and apparatus for controlled access to pressurized fluid lines and to exhausted lines. The apparatus includes a rod body having a bore; a packing fitting attached to a first end of the rod body and a ball valve attached to a second end of the rod body; a transverse arm between the first and second ends of the rod body, the transverse arm having a bore communicating the rod body bore; and a slideable rod in the bore of the rod body, in a first position of the rod a first end extends through the packing fitting to outside of the rod body and a second end is completely within the rod body, in a second position of the rod the first end extends through the packing fitting to outside of the rod body and the second end of the rod extends through and past the ball valve.Type: GrantFiled: March 7, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Robert Desrosiers, Mousa H. Ishaq, Robert L. Jourdain, Michael Lunn, Donald A. Martin
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Publication number: 20150262795Abstract: A vacuum trap, a plasma etch system using the vacuum trap and a method of cleaning the vacuum trap. The vacuum trap includes a baffle housing; and a removable baffle assembly disposed in the baffle housing, the baffle assembly comprising a set of baffle plates, the baffle plates spaced along a support rod from a first baffle plate to a last baffle plate, the baffle plates alternately disposed above and below the support rod and alternately disposed in an upper region and a lower region of the baffle housing.Type: ApplicationFiled: May 28, 2015Publication date: September 17, 2015Inventors: Joseph K. Comeau, David R. Crawford, Robert E. Desrosiers, Tracy C. Hetrick, Mousa H. Ishaq
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Patent number: 9057388Abstract: A vacuum trap, a plasma etch system using the vacuum trap and a method of cleaning the vacuum trap. The vacuum trap includes a baffle housing; and a removable baffle assembly disposed in the baffle housing, the baffle assembly comprising a set of baffle plates, the baffle plates spaced along a support rod from a first baffle plate to a last baffle plate, the baffle plates alternately disposed above and below the support rod and alternately disposed in an upper region and a lower region of the baffle housing.Type: GrantFiled: March 21, 2012Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Joseph K. Comeau, David Crawford, Robert E. Desrosiers, Tracy C. Hetrick, Mousa H. Ishaq
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Publication number: 20140251443Abstract: A method and apparatus for controlled access to pressurized fluid lines and to exhausted lines. The apparatus includes a rod body having a bore; a packing fitting attached to a first end of the rod body and a ball valve attached to a second end of the rod body; a transverse arm between the first and second ends of the rod body, the transverse arm having a bore communicating the rod body bore; and a slideable rod in the bore of the rod body, in a first position of the rod a first end extends through the packing fitting to outside of the rod body and a second end is completely within the rod body, in a second position of the rod the first end extends through the packing fitting to outside of the rod body and the second end of the rod extends through and past the ball valve.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Inventors: Robert Desrosiers, Mousa H. Ishaq, Robert L. Jourdain, Michael Lunn, Donald A. Martin
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Publication number: 20130248112Abstract: A vacuum trap, a plasma etch system using the vacuum trap and a method of cleaning the vacuum trap. The vacuum trap includes a baffle housing; and a removable baffle assembly disposed in the baffle housing, the baffle assembly comprising a set of baffle plates, the baffle plates spaced along a support rod from a first baffle plate to a last baffle plate, the baffle plates alternately disposed above and below the support rod and alternately disposed in an upper region and a lower region of the baffle housing.Type: ApplicationFiled: March 21, 2012Publication date: September 26, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph K. Comeau, David Crawford, Robert E. Desrosiers, Tracy C. Hetrick, Mousa H. Ishaq
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Patent number: 7521748Abstract: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.Type: GrantFiled: October 19, 2007Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Marshall J. Fleming, Jr., Mousa H. Ishaq, Steven M. Shank, Michael C. Triplett
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Patent number: 7342290Abstract: A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.Type: GrantFiled: November 4, 2004Date of Patent: March 11, 2008Assignee: International Business Machines CorporationInventors: Jay S. Burnham, James R. Elliott, Kenneth R. Gault, Mousa H. Ishaq, Steven M. Shank, Mary A. St. Lawrence
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Patent number: 7294554Abstract: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.Type: GrantFiled: February 10, 2006Date of Patent: November 13, 2007Assignee: International Business Machines CorporationInventors: Marshall J. Fleming, Jr., Mousa H. Ishaq, Steven M. Shank, Michael C. Triplett
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Patent number: 6855207Abstract: An intergrated closed apparatus and system for eliminating contaminants including metallic and/or hydrocarbon-containing contaminants on a surface of a semiconductor substrate. The apparatus and system include a heating chamber for heating the contaminated substrate to an elevated temperature, and an input line for purging the chamber with a chlorine-containing gas. The chlorine dissociates from the chlorine-containing gas, reacts with the contaminates, and forms volatile chloride byproducts which are removed from the heating chamber via an output line. A cooling chamber of the apparatus and system having an input line for providing a gas therein cools the substrate. A workpiece holds the substrate, which in turn, is held in position by a pedestal. The pedestal is in contact with a door that seals the closed apparatus and system, whereby the door transfers the substrate from the heating chamber to the cooling chamber, and vice versa.Type: GrantFiled: December 10, 2003Date of Patent: February 15, 2005Assignee: International Business Machines CorporationInventors: Brian P. Conchieri, David D. Dussault, Mousa H. Ishaq
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Patent number: 6838396Abstract: A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.Type: GrantFiled: March 28, 2003Date of Patent: January 4, 2005Assignee: International Business Machines CorporationInventors: Jay S. Burnham, James R. Elliott, Kenneth R. Gault, Mousa H. Ishaq, Steven M. Shank, Mary A. St. Lawrence
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Publication number: 20040192065Abstract: A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.Type: ApplicationFiled: March 28, 2003Publication date: September 30, 2004Applicant: International Business Machines CorporationInventors: Jay S. Burnham, James R. Elliott, Kenneth R. Gault, Mousa H. Ishaq, Steven M. Shank, Mary A. St. Lawrence
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Publication number: 20040118810Abstract: A method and apparatus are provided for eliminating contaminants including metallic and/or hydrocarbon-containing contaminants on a surface of a semiconductor substrate by heating a semiconductor substrate which may have contaminates on the surface thereof to an elevated temperature within an integrated closed system while simultaneously purging the integrated closed system with a chlorine-containing gas. At the elevated temperatures the chlorine dissociates from the chlorine-containing gas and reacts with the contaminates on the substrate surface to form volatile chloride byproducts with such contaminants which are removed from the integrated closed system while the substrate is continuously heated and purged with the chlorine-containing gas. Subsequently, the substrate is moved to a cooling chamber within the integrated closed system and cooled to provide a semiconductor substrate having a clean surface.Type: ApplicationFiled: December 10, 2003Publication date: June 24, 2004Applicant: International Business Machines CorporationInventors: Brian P. Conchieri, David D. Dussault, Mousa H. Ishaq
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Patent number: 6715497Abstract: A method and apparatus are provided for eliminating contaminants including metallic and/or hydrocarbon-containing contaminants on a surface of a semiconductor substrate by heating a semiconductor substrate which may have contaminants on the surface thereof to an elevated temperature within an integrated closed system while simultaneously purging the integrated closed system with a chlorine-containing gas. At the elevated temperatures the chlorine dissociates from the chlorine-containing gas and reacts with the contaminants on the substrate surface to form volatile chloride byproducts with such contaminants which are removed from the integrated closed system while the substrate is continuously heated and purged with the chlorine-containing gas. Subsequently, the substrate is moved to a cooling chamber within the integrated closed system and cooled to provide a semiconductor substrate having a clean surface.Type: GrantFiled: January 2, 2001Date of Patent: April 6, 2004Assignee: International Business Machines CorporationInventors: Brian P. Conchieri, David D. Dussault, Mousa H. Ishaq
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Patent number: 6670283Abstract: Disclosed is a method of fabricating a semiconductor device, comprising: (a) providing a bare semiconductor substrate, the substrate having a frontside and a backside; (b) forming one or more protective films on the backside of the substrate; and (c) performing one or more wafer fabrication steps. Some or all the protective films may be removed and the method repeated multiple times during fabrication of the semiconductor device.Type: GrantFiled: November 20, 2001Date of Patent: December 30, 2003Assignee: International Business Machines CorporationInventors: Faye D. Baker, Casey J. Grant, Mousa H. Ishaq, Joel M. Sharrow, James D. Weil
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Publication number: 20030157786Abstract: A method and apparatus are provided for eliminating contaminants including metallic and/or hydrocarbon-containing contaminants on a surface of a semiconductor substrate by heating a semiconductor substrate which may have contaminates on the surface thereof to an elevated temperature within an integrated closed system while simultaneously purging the integrated closed system with a chlorine-containing gas. At the elevated temperatures the chlorine dissociates from the chlorine-containing gas and reacts with the contaminates on the substrate surface to form volatile chloride byproducts with such contaminants which are removed from the integrated closed system while the substrate is continuously heated and purged with the chlorine-containing gas. Subsequently, the substrate is moved to a cooling chamber within the integrated closed system and cooled to provide a semiconductor substrate having a clean surface.Type: ApplicationFiled: January 2, 2001Publication date: August 21, 2003Applicant: International Business Machines CorporationInventors: Brian P. Conchieri, David D. Dussault, Mousa H. Ishaq
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Publication number: 20030096507Abstract: Disclosed is a method of fabricating a semiconductor device, comprising: (a) providing a bare semiconductor substrate, the substrate having a frontside and a backside; (b) forming one or more protective films on the backside of the substrate; and (c) performing one or more wafer fabrication steps. Some or all the protective films may be removed and the method repeated multiple times during fabrication of the semiconductor device.Type: ApplicationFiled: November 20, 2001Publication date: May 22, 2003Inventors: Faye D. Baker, Casey J. Grant, Mousa H. Ishaq, Joel M. Sharrow, James D. Weil
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Patent number: 4609429Abstract: A process is provided for making a conductive structure for a semiconductor circuit, such as a one device dynamic random access memory cell, which includes the steps of depositing a conductive layer on a surface of a semiconductor substrate having a given type conductivity spaced from a storage node, depositing a layer of polysilicon over the conductive layer, depositing a layer of photoresist over the polysilicon layer, defining an opening in the photoresist layer and implanting ions of a conductivity type opposite to that of the given type conductivity through the opening and the polysilicon layer into the semiconductor substrate to form therein a conductive pocket or region having the opposite type conductivity resulting in, e.g., a highly conductive bit/sense line of a memory cell.Type: GrantFiled: July 2, 1984Date of Patent: September 2, 1986Assignee: International Business Machines CorporationInventors: Mousa H. Ishaq, Wendell P. Noble, Jr.
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Patent number: 4490193Abstract: A method for diffusing a conductively determining impurity in a semiconductor substrate and making electrical contact thereto by depositing a layer of a rare earth boride material over a predetermined surface portion of the substrate and heating the substrate for a predetermined period of time at a predetermined temperature which is sufficient to cause boron from the boride material to diffuse into the adjoining portion of the substrate to modify its conductive characteristics. At the same time a good electrical ohmic contact is established between the boride material and the adjoining substrate portion while the boride material retains its conductivity even after the outdiffusion of some of its boron into the substrate during the heat treatment.Type: GrantFiled: September 29, 1983Date of Patent: December 25, 1984Assignee: International Business Machines CorporationInventors: Mousa H. Ishaq, Stanley Roberts, James G. Ryan
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Patent number: 4432035Abstract: An improved method of fabricating a stable high dielectric constant and low leakage dielectric material includes oxidizing at a temperature of about 400.degree. C. or higher a layer of a transition metal-silicon alloy having 40% to 90% transition metal by atomic weight to produce a silicate or homogeneous mixture. The mixture includes an oxide of the transition metal and silicon dioxide. The alloy may be deposited on, e.g., a semiconductor or an electrically conductive layer that is oxidation resistant, and the thickness of the mixture or oxidized alloy should be within the range of 5 to 50 nanometers. By depositing an electrically conductive layer on the homogeneous mixture, a capacitor having a high dielectric, low leakage dielectric medium is provided.Type: GrantFiled: June 11, 1982Date of Patent: February 14, 1984Assignee: International Business Machines Corp.Inventors: Ning Hsieh, Eugene A. Irene, Mousa H. Ishaq, Stanley Roberts