Patents by Inventor Mozafar Maghsoudnia

Mozafar Maghsoudnia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10651151
    Abstract: A method includes aligning a germanium feature on a first CMOS wafer with an aluminum feature on a second CMOS wafer. The aluminum feature and the germanium feature are pressed together. A eutectic bond is formed connecting the aluminum feature to the germanium feature. The eutectic bond has a melting point which is lower than the melting point of aluminum and the melting point of germanium.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 12, 2020
    Assignee: InvenSense, Inc.
    Inventors: Peter Smeys, Mozafar Maghsoudnia
  • Patent number: 10472231
    Abstract: A Micro Electro Mechanical systems (MEMS) device includes a solder bump on a substrate, a CMOS-MEMS die comprising a CMOS die and a MEMS die, and stud bumps on the CMOS die. The MEMS die is disposed between the CMOS die and the substrate. The stud bumps and the solder bumps are positioned to provide an electrical connection between the CMOS die and the substrate.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 12, 2019
    Assignee: Invensense, Inc.
    Inventors: Brian H. Kim, Haijun She, Mozafar Maghsoudnia
  • Publication number: 20190308874
    Abstract: A Micro Electro Mechanical systems (MEMS) device includes a solder bump on a substrate, a CMOS-MEMS die comprising a CMOS die and a MEMS die, and stud bumps on the CMOS die. The MEMS die is disposed between the CMOS die and the substrate. The stud bumps and the solder bumps are positioned to provide an electrical connection between the CMOS die and the substrate.
    Type: Application
    Filed: October 27, 2016
    Publication date: October 10, 2019
    Inventors: Brian H. Kim, Haijun She, Mozafar Maghsoudnia
  • Patent number: 10351419
    Abstract: Integrated microelectromechanical systems (MEMS) acoustic sensor devices are disclosed. Integrated MEMS acoustic sensor devices can comprise a MEMS acoustic sensor element and a pressure sensor within the back cavity associated with the MEMS acoustic sensor element. Integrated MEMS acoustic sensor devices can comprise a port adapted to receive acoustic waves or pressure. Methods of fabrication are also disclosed.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: July 16, 2019
    Assignee: INVENSENSE, INC.
    Inventors: Jia Gao, Brian Kim, Peter George Hartwell, Mozafar Maghsoudnia
  • Publication number: 20170334714
    Abstract: Integrated microelectromechanical systems (MEMS) acoustic sensor devices are disclosed. Integrated MEMS acoustic sensor devices can comprise a MEMS acoustic sensor element and a pressure sensor within the back cavity associated with the MEMS acoustic sensor element. Integrated MEMS acoustic sensor devices can comprise a port adapted to receive acoustic waves or pressure. Methods of fabrication are also disclosed.
    Type: Application
    Filed: May 20, 2016
    Publication date: November 23, 2017
    Inventors: Jia Gao, Brian Kim, Peter George Hartwell, Mozafar Maghsoudnia
  • Publication number: 20170330863
    Abstract: A method includes aligning a germanium feature on a first CMOS wafer with an aluminum feature on a second CMOS wafer. The aluminum feature and the germanium feature are pressed together. A eutectic bond is formed connecting the aluminum feature to the germanium feature. The eutectic bond has a melting point which is lower than the melting point of aluminum and the melting point of germanium.
    Type: Application
    Filed: July 28, 2017
    Publication date: November 16, 2017
    Inventors: Peter Smeys, Mozafar Maghsoudnia
  • Patent number: 9754922
    Abstract: Provided herein is an apparatus including a first CMOS wafer and a second CMOS wafer. A number of eutectic bonds connect the first CMOS wafer to the second CMOS wafer. The eutectic bond includes combinations where the eutectic bonding temperature is lower than the maximum temperature a CMOS circuit can withstand without being damaged during processing.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: September 5, 2017
    Assignee: InvenSense, Inc.
    Inventors: Peter Smeys, Mozafar Maghsoudnia
  • Patent number: 9611137
    Abstract: A method and system for providing a MEMS sensor integrated with a flip chip are disclosed. In a first aspect, the system comprises a MEMS sensor, at least one flip chip coupled to the MEMS sensor, and at least one through-silicon via (TSV) that electrically connects the at least one flip chip to the MEMS sensor. In a second aspect, the system comprises a MEMS sensor that includes a CMOS coupled to a MEMS structure, wherein the CMOS comprises a substrate coupled to an interconnect in contact with the MEMS structure. The system further comprises a plurality of flip chips coupled to the substrate, a plurality of TSV that electrically connect the plurality of flip chips to the interconnect, and a plurality of layers on the substrate to provide electrical connections between the plurality of flip chips and from the plurality of flip chips to at least one external component.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: April 4, 2017
    Assignee: INVENSENSE, INC.
    Inventors: Peter Smeys, Mozafar Maghsoudnia
  • Publication number: 20170044007
    Abstract: A Micro Electro Mechanical systems (MEMS) device includes a solder bump on a substrate, a CMOS-MEMS die comprising a CMOS die and a MEMS die, and stud bumps on the CMOS die. The MEMS die is disposed between the CMOS die and the substrate. The stud bumps and the solder bumps are positioned to provide an electrical connection between the CMOS die and the substrate.
    Type: Application
    Filed: October 27, 2016
    Publication date: February 16, 2017
    Inventors: Brian H. Kim, Haijun She, Mozafar Maghsoudnia
  • Patent number: 9508663
    Abstract: A Micro Electro Mechanical systems (MEMS) device includes a solder bump on a substrate, a CMOS-MEMS die comprising a CMOS die and a MEMS die, and stud bumps on the CMOS die. The MEMS die is disposed between the CMOS die and the substrate. The stud bumps and the solder bumps are positioned to provide an electrical connection between the CMOS die and the substrate.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: November 29, 2016
    Assignee: INVENSENSE, INC.
    Inventors: Brian H. Kim, Haijun She, Mozafar Maghsoudnia
  • Publication number: 20160233197
    Abstract: Provided herein is an apparatus including a first CMOS wafer and a second CMOS wafer. A number of eutectic bonds connect the first CMOS wafer to the second CMOS wafer. The eutectic bond includes combinations where the eutectic bonding temperature is lower than the maximum temperature a CMOS circuit can withstand without being damaged during processing.
    Type: Application
    Filed: February 10, 2016
    Publication date: August 11, 2016
    Inventors: Peter Smeys, Mozafar Maghsoudnia
  • Publication number: 20160060100
    Abstract: A method and system for providing a MEMS sensor integrated with a flip chip are disclosed. In a first aspect, the system comprises a MEMS sensor, at least one flip chip coupled to the MEMS sensor, and at least one through-silicon via (TSV) that electrically connects the at least one flip chip to the MEMS sensor. In a second aspect, the system comprises a MEMS sensor that includes a CMOS coupled to a MEMS structure, wherein the CMOS comprises a substrate coupled to an interconnect in contact with the MEMS structure. The system further comprises a plurality of flip chips coupled to the substrate, a plurality of TSV that electrically connect the plurality of flip chips to the interconnect, and a plurality of layers on the substrate to provide electrical connections between the plurality of flip chips and from the plurality of flip chips to at least one external component.
    Type: Application
    Filed: December 3, 2014
    Publication date: March 3, 2016
    Inventors: Peter SMEYS, Mozafar MAGHSOUDNIA
  • Publication number: 20150028432
    Abstract: A Micro Electro Mechanical systems (MEMS) device includes a solder bump on a substrate, a CMOS-MEMS die comprising a CMOS die and a MEMS die, and stud bumps on the CMOS die. The MEMS die is disposed between the CMOS die and the substrate. The stud bumps and the solder bumps are positioned to provide an electrical connection between the CMOS die and the substrate.
    Type: Application
    Filed: July 24, 2013
    Publication date: January 29, 2015
    Inventors: Brian H. Kim, Haijun She, Mozafar Maghsoudnia
  • Patent number: 7808223
    Abstract: An integrated circuit device for delivering power to a load includes a composite transistor and a composite schottky diode. The composite transistor is formed by a plurality of component transistors that have commonly coupled source terminals, commonly coupled drain terminals and commonly coupled gate terminals. The composite schottky diode is formed by a plurality of component schottky diodes that have anodes coupled in common and coupled to the source terminals of the plurality of component transistors, and for which drain terminals of the commonly coupled drain terminals constitute respective cathodes.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: October 5, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Sandeep Khanna, Mozafar Maghsoudnia
  • Patent number: 6365482
    Abstract: A method for stabilizing thin film structures fabricated on an I.C. wafer requires the performance of a rapid thermal annealing (RTA) step after the thin film material, preferably silicon-chromium (SiCr) or silicon chromium carbide (SiCrC), is sputtered onto the wafer. The RTA step stabilizes the TF and thereby increases the film's integrity. With the TF structures stabilized, the effect of subsequent high temperature process steps on the film is reduced. The stabilization method enables TF resistors thereby formed to attain a higher degree of accuracy, and thus to improve the ability with which resistors can be matched. Resistor TCR and sheet rho consistency are also improved, both within a given wafer and from wafer to wafer.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: April 2, 2002
    Assignee: Analog Devices, Inc.
    Inventor: Mozafar Maghsoudnia
  • Patent number: 6090678
    Abstract: A novel I.C. processing scheme for the fabrication of thin film features eliminates the wet etching step previously required, reducing the chip's minimum metal spacing and improving component matching capabilities and reliability. A thin film material is deposited and patterned, prior to a contact mask or platinum sputter/sinter/strip step, followed by the deposition of a protective layer. Contact mask and silicide metallization steps create contacts to the substrate, and a second contact mask step creates openings to the thin film features. The protective layer covering the thin film material allows a dry etch to be used for the final metal etch step, eliminating the need for a wet etch step and its attendant problems. The process requires no new design rules, and is easily adapted to existing products.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: July 18, 2000
    Assignee: Analog Devices, Inc.
    Inventor: Mozafar Maghsoudnia