Abstract: A method, system and computer program product for forming a netlist for an electronic circuit is disclosed. A Very High Speed Integrated Circuit Hardware Description Language (VHDL) file is created for a plurality of voltage domains. The VHDL file includes a voltage domain attribute and a logic voltage attribute for a pin of the electronic circuit. The voltage domain attribute and the logic voltage attribute for the pin are read from the VHDL file. Netlist instructions for the pin are synthesized to form a netlist for the electronic circuit. Synthesizing the netlist instructions begins with synthesizing netlist instructions within a voltage domain indicated by the voltage domain attribute and ends with synthesizing netlist instructions within a voltage domain indicated by the logic voltage attribute.

Abstract: A method and system for using a programmable driver to dynamically adjust the path delay of a circuit. The path delay adjustment circuit in the illustrative embodiments comprises two or more latches, wherein each latch receives a signal, processes the signal, and generates an output. Compare logic connected to the latches compares the outputs to determine whether the outputs are equal. A counter connected to the compare logic increments a present state of code within the counter if the compare logic determines that the outputs are not equal. A controller connected to the counter comprises a decoder which receives the incremented code from the counter and converts the incremented code to thermometer code. The controller uses the thermometer code to adjust the drive strength of a driver of at least one of the signals.

Abstract: In one embodiment a circuit, comprises a first terminal coupled to a voltage source switchable between a first voltage level and a second voltage level, a driver comprising a first inverter, a second inverter, an output stage comprising a PFET and an NFET having source drain paths connected in series across opposite power supply terminals, the PFET and NFET each having a gate electrode that switches on and off in response to a voltage applied to the gate electrode being on opposite sides of a threshold, first pulse shaping circuitry coupled to the first inverter and the PFET and comprising a first resistor and a first capacitor, the first capacitor being connected across the gate electrode of the PFET and a first of the power supply terminals, the first capacitor comprising an NFET, and second pulse shaping circuitry coupled to the second inverter and the NFET and comprising a second resistor and a second capacitor, the second resistor being connected the gate electrode of the NFET and a first of the power su

Abstract: An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. Each inverter includes a pair of switches and a resistor for connecting opposite polarity voltage sources to a separate capacitor connected in shunt with gate electrodes of the PFET and NFET. The inverters, resistors and capacitors prevent the PFET and NFET from being on simultaneously.

Abstract: An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of CMOS inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. The inverters include resistors connected to NFET and PFET devices which function as voltage controlled switched capacitors respectively connected in shunt with gate electrodes of the output stage PFET and NFET. The inverters, resistors and capacitors prevent the output stage PFET and NFET from being on simultaneously.

Abstract: An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. Each inverter includes a pair of switches and a resistor for connecting opposite polarity voltage sources to a separate capacitor connected in shunt with gate electrodes of the PFET and NFET. The inverters, resistors and capacitors prevent the PFET and NFET from being on simultaneously.

Abstract: An integrated circuit driver includes an output stage having source drain paths of PFET and NFET connected in series with each other across DC power supply terminals. A pair of CMOS inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. The inverters include resistors connected to NFET and PFET devices which function as voltage controlled switched capacitors respectively connected in shunt with gate electrodes of the output stage PFET and NFET.

Abstract: An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. Each inverter includes a pair of switches and a resistor for connecting opposite polarity voltage sources to a separate capacitor connected in shunt with gate electrodes of the PFET and NFET. The inverters, resistors and capacitors prevent the PFET and NFET from being on simultaneously.

Abstract: An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. Each inverter includes a pair of switches and a resistor for connecting opposite polarity voltage sources to a separate capacitor connected in shunt with gate electrodes of the PFET and NFET. The inverters, resistors and capacitors prevent the PFET and NFET from being on simultaneously.

Abstract: An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of CMOS inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. The inverters include resistors connected to NFET and PFET devices which function as voltage controlled switched capacitors respectively connected in shunt with gate electrodes of the output stage PFET and NFET. The inverters, resistors and capacitors prevent the output stage PFET and NFET from being on simultaneously.

Abstract: An encoding for a set of PVT calibration signals that ensures monotonicity from code step to code step and also allows many of the drive transistors to be sized the same. A calibration signal encoding that is a combination of binary and thermometer codes is disclosed. A thermometer code is used to set a course value for the impedance of the driver and a binary code is used to fine-tune the output impedance. A driver/termination that receives this encoding is also disclosed. The driver/termination has transistors controlled by the binary portion of the encoding that are each approximately multiples of two in width-to-length ratio of each other. The driver/termination also has transistors controlled by the thermometer portion of the encoding that are each approximately the same width-to-length ratio.