Abstract: The invention is notably directed to a voltage-to-time converter comprising a first interleaving stage configured to perform a sampling of an input voltage, thereby generating a first set of sampled voltage signals. The first interleaving stage is further configured to perform a first voltage-to-time conversion in an interleaved manner, thereby generating a first set of time-interleaved signals in the time domain. A second interleaving stage is configured to perform a time-to-voltage conversion of the first set of time-interleaved signals, thereby generating a second set of sampled voltage signals. The second interleaving stage is further configured perform a second voltage-to-time conversion in an interleaved manner, thereby generating a second set of time-interleaved signals in the time domain. The invention further concerns a related design structure and a related method.

Abstract: A hierarchical time step generator circuit is configured to be used for a time-based analog-to-digital converter. The hierarchical time step generator is configured to generate multiphase clock signals in response to receiving a reference clock signal. The time-based analog-to-digital converter is configured to be controlled to digitize the input signal by the multiphase clock signals. The hierarchical time step generator includes a first level time step generator configured to generate the a set of first level multiphase signals in response to receiving the reference clock signal a phase interpolator circuit configured as second level to generate second level clock signals between each of the first level clock signals and a third level configured to generate the third set of multiphase clock signals using a set of time staggered multi-phase phase locked loops synchronized to each of the second level clock signals.

Abstract: The invention relates to a control unit for controlling a data transfer between a classical processor and a quantum processor with a plurality of qubits. The control unit comprises a plurality of control and read-out circuits configured for controlling and reading out the plurality of qubits. Each of the control and read-out circuits is assigned to one or more of the qubits. A controlling of the quantum processor by the control unit comprises selectively powering on a subset of the control and read-out circuits during an instruction cycle, while ensuring that the remaining control and read-out circuits are powered off during the instruction cycle. The powered-on subset of control and read-out circuits is used to control a subset of the qubits and to read out data from the subset of qubits.

Abstract: Disclosed herein is an analog-to-digital converter circuit configured for digitizing an analog input signal. The analog-to-digital converter comprises an analog input configured for receiving the analog input signal. The analog-to-digital converter circuit further comprises at least one sub-ADC connected to the analog input signal, wherein the at least one sub-ADC is configured to output at least one encoded output vector in response to receiving the analog input signal. The analog-to-digital converter circuit further comprises a lookup circuit comprising a nested lookup table. The lookup circuit is configured to select an output value from the nested lookup table using the at least one encoded output vector, wherein the lookup circuit is configured to provide the output value as the digitization of the analog input signal.

Abstract: Disclosed herein is a hierarchical time step generator circuit configured to be used for a time-based analog-to-digital converter. The hierarchical time step generator is configured to generate multiphase clock signals in response to receiving a reference clock signal. The time-based analog-to-digital converter is configured to be controlled to digitize the input signal by the multiphase clock signals. The hierarchical time step generator comprises: a first level time step generator configured to generate the a set of first level multiphase signals in response to receiving the reference clock signal; a phase interpolator circuit configured as second level to generate second level clock signals between each of the first level clock signals; and a third level configured to generate the third set of multiphase clock signals using a set of time staggered multi-phase phase locked loops synchronized to each of the second level clock signals.

Abstract: Disclosed herein is an analog-to-digital converter circuit configured for digitizing an analog input signal. The analog-to-digital converter comprises an analog input configured for receiving the analog input signal. The analog-to-digital converter circuit further comprises at least one sub-ADC connected to the analog input signal, wherein the at least one sub-ADC is configured to output at least one encoded output vector in response to receiving the analog input signal. The analog-to-digital converter circuit further comprises a lookup circuit comprising a nested lookup table. The lookup circuit is configured to select an output value from the nested lookup table using the at least one encoded output vector, wherein the lookup circuit is configured to provide the output value as the digitization of the analog input signal.

Abstract: Provided is a low noise amplifier circuit for a quantum computer. The low noise amplifier circuit comprises a plurality of input stages, a shared output stage, and a voltage controller. Each input stage is coupled to one or more qubits. The shared output stage is coupled to the plurality of input stages. The voltage controller is coupled to the plurality of input stages and the shared output stage. The voltage controller is configured to selectively activate an input stage of the plurality of input stages in order to read a qubit coupled to the input stage.

Abstract: An electrostatic discharge (ESD) protection circuit is configured to protect a target circuit that operates in a cryogenic temperature is provided. The ESD protection circuit connects a terminal of the target circuit and a ground potential with no connection to a bias potential. When the ESD protection circuit receives a voltage potential at the terminal of the target circuit, the ESD protection circuit (i) disallows electrical current to flow through from the received voltage potential when the device is at a cryogenic temperature and (ii) allows electrical current to flow through from the received voltage potential when the device is at a room temperature.

Abstract: An electrostatic discharge (ESD) protection circuit is configured to protect a target circuit that operates in a cryogenic temperature is provided. The ESD protection circuit connects a terminal of the target circuit and a ground potential with no connection to a bias potential. When the ESD protection circuit receives a voltage potential at the terminal of the target circuit, the ESD protection circuit (i) disallows electrical current to flow through from the received voltage potential when the device is at a cryogenic temperature and (ii) allows electrical current to flow through from the received voltage potential when the device is at a room temperature.

Abstract: The invention relates to a control unit for controlling a data transfer between a classical processor and a quantum processor with a plurality of qubits. The control unit comprises a plurality of control and read-out circuits configured for controlling and reading out the plurality of qubits. Each of the control and read-out circuits is assigned to one or more of the qubits. A controlling of the quantum processor by the control unit comprises selectively powering on a subset of the control and read-out circuits during an instruction cycle, while ensuring that the remaining control and read-out circuits are powered off during the instruction cycle. The powered-on subset of control and read-out circuits is used to control a subset of the qubits and to read out data from the subset of qubits.

Abstract: A synchronous divider circuit with time-synchronized outputs. The synchronous divider circuit includes a plurality of divider stages including each a D-flip-flop circuit and a respective retiming flip-flop circuit, wherein an output terminal of the retiming flip-flop circuit of a current divider stage is connected to an input of the D-flip-flop circuit of a next divider stage, and wherein the current divider stage includes an additional retiming flip-flop circuit, wherein the output terminal of the retiming flip-flop circuit of the current divider stage is connected to an input terminal of the additional retiming flip-flop circuit of the current divider stage, so that an output signal of the additional retiming flip-flop circuit of the current divider stage and an output terminal of the retiming flip-flop circuit of the next divider stage are time-synchronized with respect to each other.