Abstract: An apparatus is configured to render graphics content to reduce latency of the graphics content. The apparatus includes a display configured to present graphics content including a first portion corresponding to an area of interest and further including a second portion. The apparatus further includes a fovea estimation engine configured to generate an indication of the area of interest based on scene information related to the graphics content. The apparatus further includes a rendering engine responsive to the fovea estimation engine. The rendering engine is configured to perform a comparison of a first result of an evaluation metric on part of the area of interest with a second result of the evaluation metric with another part of the area of interest. The rendering engine is further configured to render the graphics content using predictive adjustment to reduce latency based on the comparison.

Abstract: An apparatus is configured to render graphics content to reduce latency of the graphics content. The apparatus includes a display configured to present graphics content including a first portion corresponding to an area of interest and further including a second portion. The apparatus further includes a fovea estimation engine configured to generate an indication of the area of interest based on scene information related to the graphics content. The apparatus further includes a rendering engine responsive to the fovea estimation engine. The rendering engine is configured to perform a comparison of a first result of an evaluation metric on part of the area of interest with a second result of the evaluation metric with another part of the area of interest. The rendering engine is further configured to render the graphics content using predictive adjustment to reduce latency based on the comparison.

Abstract: Systems, methods, and computer programs are disclosed for reducing memory bandwidth via multiview compression/decompression. One embodiment is a compression method for a multiview rendering in a graphics pipeline. The method comprises receiving a first image and a second image for a multiview rendering. A difference is calculated between the first and second images. The method compresses the first image and the difference between the first and second images. The compressed first image and the compressed difference are stored in a memory. The compressed first image and the compressed difference are decompressed. The second image is generated by comparing the first image to the difference.

Abstract: An apparatus is configured to render graphics content to reduce latency of the graphics content. The apparatus includes a display configured to present graphics content including a first portion corresponding to an area of interest and further including a second portion. The apparatus further includes a fovea estimation engine configured to generate an indication of the area of interest based on scene information related to the graphics content. The apparatus further includes a rendering engine responsive to the fovea estimation engine. The rendering engine is configured to perform a comparison of a first result of an evaluation metric on part of the area of interest with a second result of the evaluation metric with another part of the area of interest. The rendering engine is further configured to render the graphics content using predictive adjustment to reduce latency based on the comparison.

Abstract: Systems, methods, and computer programs are disclosed for reducing memory bandwidth via multiview compression/decompression. One embodiment is a compression method for a multiview rendering in a graphics pipeline. The method comprises receiving a first image and a second image for a multiview rendering. A difference is calculated between the first and second images. The method compresses the first image and the difference between the first and second images. The compressed first image and the compressed difference are stored in a memory. The compressed first image and the compressed difference are decompressed. The second image is generated by comparing the first image to the difference.

Abstract: Disclosed are methods and systems for intelligent adjustment of an immersive multimedia workload in a portable computing device (“PCD”), such as a virtual reality (“VR”) or augmented reality (“AR”) workload. An exemplary embodiment monitors one or more performance indicators comprising a motion to photon latency associated with the immersive multimedia workload. Performance parameters associated with thermally aggressive processing components are adjusted to reduce demand for power while ensuring that the motion to photon latency is and/or remains optimized. Performance parameters that may be adjusted include, but are not limited to including, eye buffer resolution, eye buffer MSAA, timewarp CAC, eye buffer FPS, display FPS, timewarp output resolution, textures LOD, 6DOF camera FPS, and fovea size.

Abstract: An apparatus is configured to render graphics content to reduce latency of the graphics content. The apparatus includes a display configured to present graphics content including a first portion corresponding to an area of interest and further including a second portion. The apparatus further includes a fovea estimation engine configured to generate an indication of the area of interest based on scene information related to the graphics content. The apparatus further includes a rendering engine responsive to the fovea estimation engine. The rendering engine is configured to perform a comparison of a first result of an evaluation metric on part of the area of interest with a second result of the evaluation metric with another part of the area of interest. The rendering engine is further configured to render the graphics content using predictive adjustment to reduce latency based on the comparison.

Abstract: Systems, methods, and computer programs are disclosed for minimizing power consumption in graphics frame processing. One such method comprises: initiating graphics frame processing to be cooperatively performed by a central processing unit (CPU) and a graphics processing unit (GPU); receiving CPU activity data and GPU activity data; determining a set of available dynamic clock and voltage/frequency scaling (DCVS) levels for the GPU and the CPU; and selecting from the set of available DCVS levels an optimal combination of a GPU DCVS level and a CPU DCVS level, based on the CPU and GPU activity data, which minimizes a combined power consumption of the CPU and the GPU during the graphics frame processing.

Abstract: Systems, methods, and computer programs are disclosed for minimizing power consumption in graphics frame processing. One such method comprises: initiating graphics frame processing to be cooperatively performed by a central processing unit (CPU) and a graphics processing unit (GPU); receiving CPU activity data and GPU activity data; determining a set of available dynamic clock and voltage/frequency scaling (DCVS) levels for the GPU and the CPU; and selecting from the set of available DCVS levels an optimal combination of a GPU DCVS level and a CPU DCVS level, based on the CPU and GPU activity data, which minimizes a combined power consumption of the CPU and the GPU during the graphics frame processing.

Abstract: Methods and apparatus for accomplishing dynamic frequency/voltage control between at least two processor cores in a multi-processor device or system include receiving busy, idle and wait, time and/or frequency information from a first processor core and receiving busy, idle, wait, time and/or frequency information from a second processor core. The received busy, idle, wait, time and/or frequency information may be correlated to identify patterns of interdependence. The correlated information may be used to determine dynamic frequency/voltage control settings for the first and second processor cores to provide a performance level that accommodates interdependent processes, threads and processor cores. The correlation of received busy, idle, wait, time and/or frequency information may involve generating a consolidated busy/idle pulse train that can then be used to set the frequency or voltage of each processor core independently.

Abstract: Systems, methods, and computer programs are disclosed for managing access requests to a DRAM memory device. One embodiment includes receiving memory access pattern data for at least one of a plurality of memory clients prior to a corresponding memory transaction with a DRAM memory device. Next, it is determined, based on the received memory access pattern data, that a future transaction of a first of the plurality of memory clients may create a future page conflict with a current transaction of a second of the plurality of memory clients. The future page conflict is then resolved by interleaving access to an associated bank in the DRAM memory device by the first and second memory clients according to the received memory access pattern data.

Abstract: The present disclosure provides for systems, methods, and apparatus for image processing. These systems, methods, and apparatus may compare a current frame to at least one previous frame to determine an amount of difference. The amount of difference between the current frame and the at least one previous frame may be compared to a threshold value. Additionally, the frame rate may be adjusted based on the comparison of the amount of difference between the current frame and the at least one previous frame and the threshold value. Another example may determine an amount of perceivable difference between a current frame and at least one previous frame and adjust a frame rate based on the determined amount of perceivable difference between the current frame and the at least one previous frame.

Abstract: Methods and apparatus for controlling at least two processing cores in a multi-processor device or system include accessing an operating system run queue to generate virtual pulse trains for each core and correlating the virtual pulse trains to identify patterns of interdependence. The correlated information may be used to determine dynamic frequency/voltage control settings for the first and second processing cores to provide a performance level that accommodates interdependent processes, threads and processing cores.

Abstract: Methods and apparatus for accomplishing dynamic frequency/voltage control between at least two processor cores in a multi-processor device or system include receiving busy, idle and wait, time and/or frequency information from a first processor core and receiving busy, idle, wait, time and/or frequency information from a second processor core. The received busy, idle, wait, time and/or frequency information may be correlated to identify patterns of interdependence. The correlated information may be used to determine dynamic frequency/voltage control settings for the first and second processor cores to provide a performance level that accommodates interdependent processes, threads and processor cores. The correlation of received busy, idle, wait, time and/or frequency information may involve generating a consolidated busy/idle pulse train that can then be used to set the frequency or voltage of each processor core independently.