Patents by Inventor Mrinal Bose

Mrinal Bose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10330728
    Abstract: A method for minimizing a test set for optimal coverage is disclosed. The method includes generating a first test set which is both an empty and minimal test set. Then, generating a second test set with a predetermined number of tests. Further, partitioning the second test set into a control test set and an experiment test set. Subsequently, providing a list of tests for coverage by merging the control test set with the first test set to form a merged list of sets.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: June 25, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mrinal Bose, James Longino, Laxmi Narayana Yakkala
  • Publication number: 20160349317
    Abstract: A method for minimizing a test set for optimal coverage is disclosed. The method includes generating a first test set which is both an empty and minimal test set. Then, generating a second test set with a predetermined number of tests. Further, partitioning the second test set into a control test set and an experiment test set. Subsequently, providing a list of tests for coverage by merging the control test set with the first test set to form a merged list of sets.
    Type: Application
    Filed: July 17, 2015
    Publication date: December 1, 2016
    Inventors: Mrinal BOSE, James LONGINO, Laxmi Narayana YAKKALA
  • Patent number: 9363526
    Abstract: An apparatus, computer readable medium, and method of compressing images generated on an image generating device, the method including responsive to a generated image and position and orientation data associated with an image generating device which generated the image, selecting a previously generated image having a similar position and a similar orientation as the generated image; and if a comparison between the selected previously generated image and the generated image indicates the difference between one of the previously generated images and the generated image is less than a threshold difference, then compressing the generated image using the previously generated image. The method may include generating the generated image from light incident to the image generating device, and generating the position and orientation associated with the image generating device.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: June 7, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mrinal Bose
  • Publication number: 20150382007
    Abstract: An apparatus, computer readable medium, and method of compressing images generated on an image generating device, the method including responsive to a generated image and position and orientation data associated with an image generating device which generated the image, selecting a previously generated image having a similar position and a similar orientation as the generated image; and if a comparison between the selected previously generated image and the generated image indicates the difference between one of the previously generated images and the generated image is less than a threshold difference, then compressing the generated image using the previously generated image. The method may include generating the generated image from light incident to the image generating device, and generating the position and orientation associated with the image generating device.
    Type: Application
    Filed: September 8, 2015
    Publication date: December 31, 2015
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventor: Mrinal Bose
  • Patent number: 9154805
    Abstract: An apparatus, computer readable medium, and method of compressing images generated on an image generating device, the method including responsive to a generated image and position and orientation data associated with an image generating device which generated the image, selecting a previously generated image having a similar position and a similar orientation as the generated image; and if a comparison between the selected previously generated image and the generated image indicates the difference between one of the previously generated images and the generated image is less than a threshold difference, then compressing the generated image using the previously generated image. The method may include generating the generated image from light incident to the image generating device, and generating the position and orientation associated with the image generating device.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 6, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mrinal Bose
  • Publication number: 20150052174
    Abstract: Exemplary embodiments for adaptive binning of verification data comprise defining in a memory by at least one processor a data organization tree having a self-modifying bin structure that automatically modifies in response to input raw verification data; responsive to receiving a stream of verification data, identifying patterns in the verification data based on business knowledge of subcategories of the data; and using the data organization tree to automatically bin together the verification data that match the identified patterns to provide an aggregate view of the verification data.
    Type: Application
    Filed: January 30, 2014
    Publication date: February 19, 2015
    Inventor: Mrinal Bose
  • Publication number: 20140072028
    Abstract: An apparatus, computer readable medium, and method of compressing images generated on an image generating device, the method including responsive to a generated image and position and orientation data associated with an image generating device which generated the image, selecting a previously generated image having a similar position and a similar orientation as the generated image; and if a comparison between the selected previously generated image and the generated image indicates the difference between one of the previously generated images and the generated image is less than a threshold difference, then compressing the generated image using the previously generated image. The method may include generating the generated image from light incident to the image generating device, and generating the position and orientation associated with the image generating device.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventor: Mrinal Bose
  • Patent number: 8234618
    Abstract: A test system collects passing event data and failing event data, and merges the collected data into passing subsequences and failing subsequences, respectively. The test system identifies an overlap area between the passing subsequence and the failing subsequence in regards to time slices and tracepoint slices, and creates passing transactions and failing transactions using the event data corresponding to the overlap area. Next, the test system detects a timing discrepancy between the first passing transaction relative to the second passing transaction compared with the first failing transaction relative to the second failing transaction. The test system then reports the detected timing discrepancy, which allows a test engineer to perturb the test program in order to more frequently catch intermittent failures caused by asynchronous timing conditions.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: July 31, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mrinal Bose, Jayanta Bhadra, Hillel Miller, Edward L. Swarthout, Ekaterina A. Trofimova
  • Patent number: 7945418
    Abstract: An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set of transactors sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: May 17, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mrinal Bose, Jayanta Bhadra, Kenneth G. Davis, Yaniv Fais, Sharon Goldschlager, Amit Hermony, Hillel Miller, Prashant U. Naphade, Pankaj Sharma, Robert S. Slater
  • Publication number: 20110107146
    Abstract: A test system collects passing event data and failing event data, and merges the collected data into passing subsequences and failing subsequences, respectively. The test system identifies an overlap area between the passing subsequence and the failing subsequence in regards to time slices and tracepoint slices, and creates passing transactions and failing transactions using the event data corresponding to the overlap area. Next, the test system detects a timing discrepancy between the first passing transaction relative to the second passing transaction compared with the first failing transaction relative to the second failing transaction. The test system then reports the detected timing discrepancy, which allows a test engineer to perturb the test program in order to more frequently catch intermittent failures caused by asynchronous timing conditions.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 5, 2011
    Inventors: Mrinal Bose, Jayanta Bhadra, Hillel Miller, Edward L. Swarthout, Ekaterina A. Trofimova
  • Publication number: 20100153053
    Abstract: An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor.
    Type: Application
    Filed: December 15, 2008
    Publication date: June 17, 2010
    Inventors: Mrinal Bose, Jayanta Bhadra, Kenneth G. Davis, Yaniv Fais, Sharon Goldschlager, Amit Hermony, Hillel Miller, Prashant U. Naphade, Pankaj Sharma, Robert S. Slater